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? 2009-2011 microchip technology inc. ds61156g pic32mx5xx/6xx/7xx family data sheet high-performance, usb, can and ethernet 32-bit flash microcontrollers free datasheet http://www.datasheet-pdf.com/
ds61156g-page 2 ? 2009-2011 microchip technology inc. information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, mi wi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009-2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-150-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semico nductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection featur e may be a violation of the digi tal millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 3 pic32mx5xx/6xx/7xx high-performance 32-bit risc cpu: ?mips32 ? m4k ? 32-bit core with 5-stage pipeline ? 80 mhz maximum frequency ? 1.56 dmips/mhz (dhrystone 2.1) performance at zero wait state flash access ? single-cycle multiply and high-performance divide unit ? mips16e ? mode for up to 40% smaller code size ? two sets of 32 core register files (32-bit) to reduce interrupt latency ? prefetch cache module to speed execution from flash microcontroller features: ? operating voltage range of 2.3v to 3.6v ? 64k to 512k flash memory (plus an additional 12 kb of boot flash) ? 16k to 128k sram memory ? pin-compatible with most pic24/dspic ? dsc devices ? multiple power management modes ? multiple interrupt vectors with individually programmable priority ? fail-safe clock monitor mode ? configurable watchdog timer with on-chip low-power rc oscillator for reliable operation peripheral features: ? atomic set, clear and invert operation on select peripheral registers ? up to 8-channels of hard ware dma with automatic data size detection ? usb 2.0-compliant full-speed device and on-the-go (otg) controller: - dedicated dma channels ? 10/100 mbps ethernet mac with mii and rmii interface: - dedicated dma channels ? can module: - 2.0b active with devicenet? addressing support - dedicated dma channels ? 3 mhz to 25 mhz crystal oscillator peripheral features (continued): ? internal 8 mhz and 32 khz oscillators ? six uart modules with: - rs-232, rs-485 and lin support -irda ? with on-chip hardware encoder and decoder ? up to four spi modules ? up to five i 2 c? modules ? separate plls for cpu and usb clocks ? parallel master and sl ave port (pmp/psp) with 8-bit and 16-bit data, and up to 16 address lines ? hardware real-time clock and calendar (rtcc) ? five 16-bit timers/counters (two 16-bit pairs combine to create two 32-bit timers) ? five capture inputs ? five compare/pwm outputs ? five external interrupt pins ? high-speed i/o pins capable of toggling at up to 80 mhz ? high-current sink/source (18 ma/18 ma) on all i/o pins ? configurable open-drain ou tput on digital i/o pins debug features: ? two programming and debugging interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire mips ? standard enhanced joint test action group (jtag) interface ? unintrusive hardware-based instruction trace ? ieee standard 1149.2 compatible (jtag) boundary scan analog features: ? up to 16-channel, 10-bit analog-to-digital converter: - 1 msps conversion rate - conversion available during sleep and idle ? two analog comparators high-performance, usb, can and ethernet 32-bit flash microcontrollers free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 4 ? 2009-2011 microchip technology inc. table 1: pic32 usb and can ? features usb and can device pins program memory (kb) data memory (kb) usb can timers/capture/compare dma channels (programmable/ dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx534f064h 64 64 + 12 (1) 16 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr PIC32MX564F064H 64 64 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx564f128h 64 128 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx575f256h 64 256 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx575f512h 64 512 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx534f064l 100 64 + 12 (1) 16 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx564f064l 100 64 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx564f128l 100 128 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx575f256l 100 256 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx575f512l 100 512 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg legend: pf, pt = tqfp mr = qfn bg = xbga note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section 32.0 ?packaging information? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 5 pic32mx5xx/6xx/7xx table 2: pic32 usb and ethernet ? features usb and ethernet device pins program memory (kb) data memory (kb) usb ethernet timers/capture/compare dma channels (programmable/ dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx664f064h 64 64 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx664f128h 64 128 + 12 (1) 32 1 1 5/5/5 4/4 6 3 4 16 2 yes yes no pt, mr pic32mx675f256h 64 256 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx675f512h 64 512 + 12 (1) 64 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx695f512h 64 512 + 12 (1) 128 1 1 5/5/5 8/4 6 3 4 16 2 yes yes no pt, mr pic32mx664f064l 100 64 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx664f128l 100 128 + 12 (1) 32 1 1 5/5/5 4/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx675f256l 100 256 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx675f512l 100 512 + 12 (1) 64 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx695f512l 100 512 + 12 (1) 128 1 1 5/5/5 8/4 6 4 5 16 2 yes yes yes pt, pf, bg legend: pf, pt = tqfp mr = qfn bg = xbga note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section 32.0 ?packaging information? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 6 ? 2009-2011 microchip technology inc. table 3: pic32 usb, ethernet and can ? features usb, ethernet and can device pins program memory (kb) data memory (kb) usb ethernet can timers/capture/compare dma channels (programmable/ dedicated) uart (2,3) spi (3) i 2 c? (3) 10-bit 1 msps adc (channels) comparators pmp/psp jtag trace packages (4) pic32mx764f128h 64 128 + 12 (1) 32 1 1 1 5/5/5 4/6 6 3 4 16 2 yes yes no pt, mr pic32mx775f256h 64 256 + 12 (1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr pic32mx775f512h 64 512 + 12 (1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr pic32mx795f512h 64 512 + 12 (1) 128 1 1 2 5/5/5 8/8 6 3 4 16 2 yes yes no pt, mr pic32mx764f128l 100 128 + 12 (1) 32 1 1 1 5/5/5 4/6 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx775f256l 100 256 + 12 (1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx775f512l 100 512 + 12 (1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg pic32mx795f512l 100 512 + 12 (1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 yes yes yes pt, pf, bg legend: pf, pt = tqfp mr = qfn bg = xbga note 1: this device features 12 kb boot flash memory. 2: cts and rts pins may not be available for all uart modules. refer to the ? pin diagrams ? section for more information. 3: some pins between the uart, spi and i 2 c modules may be shared. refer to the ? pin diagrams ? section for more information. 4: refer to section 32.0 ?packaging information? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 7 pic32mx5xx/6xx/7xx pin diagrams 64-pin qfn (1) = pins are up to 5v tolerant note 1: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. pic32mx575f256h pmd5/re5 pmd6/re6 pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/ocfb/pmall/pma0/cn12/rb15 v ss av ss cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 sck3/u4tx/u1rts /oc2/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 c1rx/rf0 v cap /v core pmd0/re0 c1tx/rf1 cn16/rd7 v dd sosci/cn1/rc13 oc1/int0/rd0 scl1/ic3/pmcs2/pma15/int3/rd10 ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/ic1/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx575f512h pic32mx534f064h PIC32MX564F064H pic32mx564f128h free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 8 ? 2009-2011 microchip technology inc. pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant pic32mx675f512h pic32mx695f512h pic32mx675f256h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rtsu2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally. pic32mx664f064h pic32mx664f128h free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 9 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclkpmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd pic32mx795f512h pic32mx775f256h pic32mx775f512h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/c2tx/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/c2rx/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 10 ? 2009-2011 microchip technology inc. pin diagrams (continued) 64-pin qfn (1) = pins are up to 5v tolerant etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclkpmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd pic32mx764f128h 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss note 1: the metal plane at the bottom of th e device is not connected to any pins and is recommended to be connected to v ss externally. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 11 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx575f256h pmd5/re5 pmd6/re6 pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/ocfb/pmall/ pma0/cn12/rb15 v ss av ss cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 sck3/u4tx/u1rts /oc2/rd1 pmd4/re4 pmd3/re3 pmd2/re2 pmd1/re1 c1rx/rf0 v cap /v core pmd0/re0 c1tx/rf1 cn16/rd7 v dd sosci/cn1/rc13 oc1/int0/rd0 scl1/ic3/pmcs2/pm a15/int3/rd10 ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/ic1/int1/rd8 ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx575f512h pic32mx534f064h PIC32MX564F064H pic32mx564f128h free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 12 ? 2009-2011 microchip technology inc. pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx675f512h pic32mx695f512h pic32mx675f256h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss pic32mx664f064h pic32mx664f128h free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 13 pic32mx5xx/6xx/7xx pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx795f512h pic32mx775f256h pic32mx775f512h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/c2tx/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/c2rx/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 14 ? 2009-2011 microchip technology inc. pin diagrams (continued) 64-pin tqfp = pins are up to 5v tolerant pic32mx764f128h etxen/pmd5/re5 etxd0/pmd6/re6 etxd1/pmd7/re7 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/v ref -/cv ref -/cn3/rb1 pged1/an0/v ref +/cv ref +/pma6/cn2/rb0 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr v ss 64 63 62 61 60 59 58 57 56 55 3 4 5 7 8 9 10 11 1 2 6 54 14 15 16 12 13 53 52 51 50 49 aetxen/etxerr/cn15/rd6 pmrd/cn14/rd5 oc5/ic5/pmwr/cn13/rd4 scl3/sdo3/u1tx/oc4/rd3 sda3/sdi3/u1rxu1rx/oc3/rd2 emdio/aemdio/sck3/u4tx/u1rts /oc2/rd1 erxerr/pmd4/re4 erxclk/erefclk/pmd3/re3 erxdv/ecrsdv/pmd2/re2 erxd0/pmd1/re1 c1rx/aetxd1/erxd3/rf0 v cap /v core erxd1/pmd0/re0 c1tx/aetxd0/erxd2/rf1 etxclk/aerxerr/cn16/rd7 v dd 22 23 24 25 26 27 28 29 30 31 40 39 38 37 36 35 34 33 42 41 32 43 17 18 19 20 21 45 44 47 46 48 av dd an8/ss4 /u5rx/u2cts /c1out/rb8 an9/c2out/pma7/rb9 tms/an10/cv refout /pma13/rb10 tdo/an11/pma12/rb11 v dd pgec2/an6/ocfa/rb6 pged2/an7/rb7 ac1rx/scl5/sdo4/u2tx/pma8/cn18/rf5 ac1tx/sda5/sdi4/u2rx/pma9/cn17/rf4 tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/sck4/u5tx/u2rts /pmalh/pma1/rb14 an15/emdc/aemdc/ocfb/pmall/pma0/cn12/rb15 v ss av ss sosci/cn1/rc13 oc1/int0/rd0 ecol/aecrsdv/scl1/ic3/pmcs2/pma15/int3/rd10 aerxd0/etxd2/ss3 /u4rx/u1cts /sda1/ic2/int2/rd9 rtcc/aerxd1/etxd3/ic1/int1/rd8 ecrs/aerefclk/ic4/pmcs1/pma14/int4/rd11 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus usbid/rf3 d-/rg3 sosco/t1ck/cn0/rc14 vss free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 15 pic32mx5xx/6xx/7xx pin diagrams (continued) pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 pmd13/cn19/rd13 ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/pmd11/rf0 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2 /rd9 rtcc/ic1/rd8 ic4/pmcs1/pma14/rd11 sda1/int4/ra15 scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/pma6/ra10 v ref -/cv ref -/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 ss3 /u4rx/u1cts /cn20/rd14 sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 int1/re8 int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 sda4/sdi2/u3rx/pma4/cn9/rg7 scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd rg15 ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr an12/pma11/rb12 an13/pma10/rb13 an14/pmalh/pma1/rb14 an15/ocfb/pmall/pma0/cn12/rb15 pmd9/rg1 c1tx/pmd10/rf1 v dd pmd14/cn15/rd6 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss v ss v cap /v core tdi/ra4 tck/ra1 100-pin tqfp pmd15/cn16/rd7 = pins are up to 5v tolerant 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 1 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 27 46 47 48 49 55 54 53 52 51 50 26 pic32mx575f512l 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 pic32mx575f256l pic32mx534f064l pic32mx564f064l pic32mx564f128l free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 16 ? 2009-2011 microchip technology inc. pin diagrams (continued) 100-pin tqfp pic32mx675f512l pic32mx695f512l pic32mx675f256l = pins are up to 5v tolerant pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr etxerr/pmd9/rg1 etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 ss1/ ic2/rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd11 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ss4 /u5rx/u2cts /rf12 sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 sck1/ic3/pmcs2/pma15/rd10 pic32mx664f064l pic32mx664f128l pgec2/an6/ocfa/rb6 26 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 17 pic32mx5xx/6xx/7xx pin diagrams (continued) 100-pin tqfp = pins are up to 5v tolerant pic32mx795f512l pic32mx775f256l pic32mx775f512l pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 c2rx/pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/ac2tx/rc2 t4ck/ac2rx/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr c2tx/etxerr/pmd9/rg1 c1tx/etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2 / rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd1 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 26 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 18 ? 2009-2011 microchip technology inc. pin diagrams (continued) 100-pin tqfp = pins are up to 5v tolerant pic32mx764f128l pmrd/cn14/rd5 oc5/pmwr/cn13/rd4 etxd3/pmd13/cn19/rd13 etxd2/ic5/pmd12/rd12 oc4/rd3 oc3/rd2 oc2/rd1 trd3/ra7 trclk/ra6 pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 pmd8/rg0 pmd4/re4 pmd3/re3 c1rx/etxd1/pmd11/rf0 pmd5/re5 pmd6/re6 pmd7/re7 t2ck/rc1 t3ck/rc2 t4ck/rc3 t5ck/sdi1/rc4 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 v dd tms/ra0 aerxd0/int1/re8 aerxd1/int2/re9 an5/c1in+/v buson /cn7/rb5 an4/c1in-/cn6/rb4 an3/c2in+/cn5/rb3 an2/c2in-/cn4/rb2 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 erxdv/aerxdv/ecrsdv/aecrsdv/scl4/sdo2/u3tx/pma3/cn10/rg8 pgec1/an1/cn3/rb1 pged1/an0/cn2/rb0 v dd aerxerr/rg15 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/u3cts /pma2/cn11/rg9 mclr etxerr/pmd9/rg1 c1tx/etxd0/pmd10/rf1 v dd etxen/pmd14/cn15/rd6 v ss v cap /v ddcore etxclk/pmd15/cn16/rd7 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 1 24 23 25 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 sosci/cn1/rc13 sdo1/oc1/int0/rd0 sck1/ic3/pmcs2/pma15/rd10 ss1/ ic2 / rd9 rtcc/emdio/aemdio/ic1/rd8 emdc/aemdc/ic4/pmcs1/pma14/rd1 aetxen/sda1/int4/ra15 aetxclk/scl1/int3/ra14 osc2/clko/rc15 osc1/clki/rc12 v dd d+/rg2 v usb v bus scl3/sdo3/u1tx/rf8 d-/rg3 sda3/sdi3/u1rx/rf2 usbid/rf3 v ss sosco/t1ck/cn0/rc14 v ref +/cv ref +/aerxd3/pma6/ra10 v ref -/cv ref -/aerxd2/pma7/ra9 av dd av ss an8/c1out/rb8 an9/c2out/rb9 an10/cv refout /pma13/rb10 an11/erxerr/aetxerr/pma12/rb11 v dd ac1rx/ss4 /u5rx/u2cts /rf12 ac1tx/sck4/u5tx/u2rts /rf13 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 aetxd1/sck3/u4tx/u1rts /cn21/rd15 v dd v ss pgec2/an6/ocfa/rb6 pged2/an7/rb7 scl5/sdo4/u2tx/pma8/cn18/rf5 sda5/sdi4/u2rx/pma9/cn17/rf4 an12/erxd0/aecrs/pma11/rb12 an13/erxd1/aecol/pma10/rb13 an14/erxd2/aetxd3/pmalh/pma1/rb14 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 tdo/ra5 sda2/ra3 scl2/ra2 v ss v ss tdi/ra4 tck/ra1 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 72 71 70 69 68 67 66 75 74 73 58 57 27 46 47 48 49 55 54 53 52 51 50 26 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 19 pic32mx5xx/6xx/7xx pin diagrams (continued) 121-pin xbga (1) 1234567891011 a re4 re3 rg13 re0 rg0 rf1 v dd v ss rd12 rd2 rd1 b nc rg15 re2 re1 ra7 rf0 v cap / v core rd5 rd3 v ss rc14 c re6 v dd rg12 rg14 ra6 nc rd7 rd4 v dd rc13 rd11 d rc1 re7 re5 v ss v ss nc rd6 rd13 rd0 nc rd10 e rc4 rc3 rg6 rc2 v dd rg1 v ss ra15 rd8 rd9 ra14 f mclr rg8 rg9 rg7 v ss nc nc v dd rc12 v ss rc15 g re8 re9 ra0 nc v dd v ss v ss nc ra5 ra3 ra4 h rb5 rb4 v ss v dd nc v dd nc v bus v usb rg2 ra2 j rb3 rb2 rb7 av dd rb11 ra1 rb12 nc nc rf8 rg3 k rb1 rb0 ra10 rb8 nc rf12 rb14 v dd rd15 rf3 rf2 l rb6 ra9 av ss rb9 rb10 rf13 rb13 rb15 rd14 rf4 rf5 pic32mx575f256l note 1: refer to table 4 , ta b l e 5 and ta b l e 6 for full pin names. = pins are up to 5v tolerant pic32mx795f512l pic32mx575f512l pic32mx675f512l pic32mx695f512l pic32mx675f256l pic32mx775f256l pic32mx775f512l pic32mx534f064l pic32mx564f064l pic32mx564f128l pic32mx664f064l pic32mx664f128l pic32mx764f128l free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 20 ? 2009-2011 microchip technology inc. table 4: pin names: pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pi c32mx575f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 c1tx/pmd10/rf1 f2 scl4/sdo2/u3tx/pma3/cn10/rg8 a7 v dd f3 ss2 /u6rx/u3cts /pma2/cn11/rg9 a8 v ss f4 sda4/sdi2/u3rx/pma4/cn9/rg7 a9 ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 int1/re8 b6 c1rx/pmd11/rf0 g2 int2/re9 b7 v cap /v core g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 sck2/u6txu6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/pma6/ra10 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 21 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/pma10/rb13 k9 sck3/u4tx/u1rts /cn21/rd15 l8 an15/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/pma7/ra9 table 4: pin names: pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pic32mx575 f512l devices (continued) pin number full pin name pin number full pin name free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 22 ? 2009-2011 microchip technology inc. table 5: pin names: pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/emdio/aemdio/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 etxd0/pmd10/rf1 f2 erxdv/aerxdv/ecrsdv/aecrsdv//scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk//ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap /v core g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11/erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 23 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 5: pin names: pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices (continued) pin number full pin name pin number full pin name free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 24 ? 2009-2011 microchip technology inc. table 6: pin names: pic32m x775f256l, pic32mx775f512l and pic32mx795f512l devices pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/em dio/aemdi o/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 c2rx/pmd8/rg0 f1 mclr a6 c1tx/etxd0/pmd10/rf1 f2 erxdv/aer xdv/ecrsdv/aecrsdv/scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 c1rx/etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap /v core g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11 /erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/ac2rx/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/ac2tx/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 c2tx/etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 25 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 6: pin names: pic32m x775f256l, pic32mx775f512l and pic32mx795f512l devices (continued) pin number full pin name pin number full pin name free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 26 ? 2009-2011 microchip technology inc. table 7: pin name: pi c32mx764f128l device pin number full pin name pin number full pin name a1 pmd4/re4 e8 aetxen/sda1/int4/ra15 a2 pmd3/re3 e9 rtcc/em dio/aemdi o/ic1/rd8 a3 trd0/rg13 e10 ss1 /ic2/rd9 a4 pmd0/re0 e11 aetxclk/scl1/int3/ra14 a5 pmd8/rg0 f1 mclr a6 c1tx/etxd0/pmd10/rf1 f2 erxdv/aer xdv/ecrsdv/aecrsdv/scl4/sdo2/ u3tx/pma3/cn10/rg8 a7 v dd f3 erxclk/aerxclk/erefclk/aerefclk/ss2 /u6rx/ u3cts /pma2/cn11/rg9 a8 v ss f4 ecrs/sda4/sdi2/u3rx/pma4/cn9/rg7 a9 etxd2/ic5/pmd12/rd12 f5 v ss a10 oc3/rd2 f6 no connect (nc) a11 oc2/rd1 f7 no connect (nc) b1 no connect (nc) f8 v dd b2 aerxerr/rg15 f9 osc1/clki/rc12 b3 pmd2/re2 f10 v ss b4 pmd1/re1 f11 osc2/clko/rc15 b5 trd3/ra7 g1 aerxd0/int1/re8 b6 c1rx/etxd1/pmd11/rf0 g2 aerxd1/int2/re9 b7 v cap /v core g3 tms/ra0 b8 pmrd/cn14/rd5 g4 no connect (nc) b9 oc4/rd3 g5 v dd b10 v ss g6 v ss b11 sosco/t1ck/cn0/rc14 g7 v ss c1 pmd6/re6 g8 no connect (nc) c2 v dd g9 tdo/ra5 c3 trd1/rg12 g10 sda2/ra3 c4 trd2/rg14 g11 tdi/ra4 c5 trclk/ra6 h1 an5/c1in+/v buson /cn7/rb5 c6 no connect (nc) h2 an4/c1in-/cn6/rb4 c7 etxclk/pmd15/cn16/rd7 h3 v ss c8 oc5/pmwr/cn13/rd4 h4 v dd c9 v dd h5 no connect (nc) c10 sosci/cn1/rc13 h6 v dd c11 emdc/aemdc/ic4/pmcs1/pma14/rd11 h7 no connect (nc) d1 t2ck/rc1 h8 v bus d2 pmd7/re7 h9 v usb d3 pmd5/re5 h10 d+/rg2 d4 v ss h11 scl2/ra2 d5 v ss j1 an3/c2in+/cn5/rb3 d6 no connect (nc) j2 an2/c2in-/cn4/rb2 d7 etxen/pmd14/cn15/rd6 j3 pged2/an7/rb7 d8 etxd3/pmd13/cn19/rd13 j4 av dd d9 sdo1/oc1/int0/rd0 j5 an11 /erxerr/aetxerr/pma12/rb11 d10 no connect (nc) j6 tck/ra1 d11 sck1/ic3/pmcs2/pma15/rd10 j7 an12/erxd0/aecrs/pma11/rb12 e1 t5ck/sdi1/rc4 j8 no connect (nc) e2 t4ck/rc3 j9 no connect (nc) e3 ecol/sck2/u6tx/u3rts /pma5/cn8/rg6 j10 scl3/sdo3/u1tx/rf8 e4 t3ck/rc2 j11 d-/rg3 e5 v dd k1 pgec1/an1/cn3/rb1 e6 etxerr/pmd9/rg1 k2 pged1/an0/cn2/rb0 e7 v ss k3 v ref +/cv ref +/aerxd3/pma6/ra10 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 27 pic32mx5xx/6xx/7xx k4 an8/c1out/rb8 l3 av ss k5 no connect (nc) l4 an9/c2out/rb9 k6 ac1rx/ss4 /u5rx/u2cts /rf12 l5 an10/cv refout /pma13/rb10 k7 an14/erxd2/aetxd3/pmalh/pma1/rb14 l6 ac1tx/sck4/u5tx/u2rts /rf13 k8 v dd l7 an13/erxd1/aecol/pma10/rb13 k9 aetxd1/sck3/u4tx/u1rts /cn21/rd15 l8 an15/erxd3/aetxd2/ocfb/pmall/pma0/cn12/rb15 k10 usbid/rf3 l9 aetxd0/ss3 /u4rx/u1cts /cn20/rd14 k11 sda3/sdi3/u1rx/rf2 l10 sd a5/sdi4/u2rx/pma9/cn17/rf4 l1 pgec2/an6/ocfa/rb6 l11 scl5/sdo4/u2tx/pma8/cn18/rf5 l2 v ref -/cv ref -/aerxd2/pma7/ra9 table 7: pin name: pic32mx7 64f128l device (continued) pin number full pin name pin number full pin name free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 28 ? 2009-2011 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ........................................................... 31 2.0 guidelines for getting started wi th 32-bit microcontrollers ................................................................. ....................................... 43 3.0 cpu......................................................................................................................... ................................................................... 49 4.0 memory organization ......................................................................................................... ........................................................ 55 5.0 flash program memory ........................................................................................................ .................................................... 117 6.0 resets ...................................................................................................................... ................................................................ 119 7.0 interrupt controller ........................................................................................................ ........................................................... 121 8.0 oscillator configuration .................................................................................................... ........................................................ 125 9.0 prefetch cache.............................................................................................................. ........................................................... 127 10.0 direct memory access (dma) controller ...................................................................................... ........................................... 129 11.0 usb on-the-go (otg)........................................................................................................ .................................................... 131 12.0 i/o ports .................................................................................................................. ................................................................. 133 13.0 timer1 ..................................................................................................................... ................................................................. 135 14.0 timer2/3, timer4/5 ......................................................................................................... .......................................................... 137 15.0 input capture.............................................................................................................. .............................................................. 139 16.0 output compare............................................................................................................. .......................................................... 141 17.0 serial peripheral interface (spi).......................................................................................... ..................................................... 143 18.0 inter-integrated circuit? (i 2 c?) ............................................................................................................................ .................. 145 19.0 universal asynchronous rece iver transmitter (uart) ......................................................................... .................................. 147 20.0 parallel master port (pmp)................................................................................................. ...................................................... 149 21.0 real-time clock and calendar (rtcc) ........................................................................................ ........................................... 151 22.0 10-bit analog-to-digital converter (adc) ................................................................................... .............................................. 153 23.0 controller area network (can) .............................................................................................. .................................................. 155 24.0 ethernet controller ........................................................................................................ ........................................................... 157 25.0 comparator ................................................................................................................. ............................................................. 159 26.0 comparator voltage reference (cv ref ).............................................................................................................................. .... 161 27.0 power-saving features ..................................................................................................... ...................................................... 163 28.0 special features ........................................................................................................... ........................................................... 165 29.0 instruction set ............................................................................................................ .............................................................. 177 30.0 development support........................................................................................................ ....................................................... 179 31.0 electrical characteristics ................................................................................................. ......................................................... 183 32.0 packaging information...................................................................................................... ........................................................ 225 the microchip web site ......................................................................................................... ............................................................ 253 customer change notification service ........................................................................................... ................................................... 253 customer support ............................................................................................................... ............................................................... 253 reader response ................................................................................................................ .............................................................. 254 product identification system.................................................................................................. ........................................................... 255 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 29 pic32mx5xx/6xx/7xx to our valued customers it is our intention to provide our valued customers with t he best documentation possible to ensure successful use of your microchip products. to this end, we will continue to im prove our publications to bett er suit your needs. our pub- lications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this p ublication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. the last character of th e literature number is the version number, (e.g., ds30000a is version a of doc- ument ds30000). errata an errata sheet, describing minor operational differenc es from the data sheet and recommended workarounds, may exist for current devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature num- ber) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 30 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 31 pic32mx5xx/6xx/7xx 1.0 device overview this document contains devic e-specific information for pic32mx5xx/6xx/7xx devices. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the pic32mx5xx/6xx/7xx family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. figure 1-1: block diagram (1,2) note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: some features are not available on all device variants. 2: bor functionality is provided when t he on-board voltage regulator is enabled. uart1-6 comparators porta portd porte portf portg portb cn1-22 jtag priority dmac icd mips32 ? m4k ? is ds ejtag int bus matrix prefetch data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 32 peripheral bus clocked by pbclk program flash memory controller 32 module 32 32 interrupt controller bscan portc pmp i2c1-5 spi1-4 ic1-5 pwm oc1-5 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap /v core osc/s osc oscillators pll dividers sysclk pbclk peripheral bus clocked by sysclk usb pll-usb usbclk 32 rtcc 10-bit adc timer1-5 32 32 can1, can2 ethernet 32 32 cpu core free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 32 ? 2009-2011 microchip technology inc. table 1-1: pinout i/o descriptions pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga an0 16 25 k2 i analog analog input channels. an1 15 24 k1 i analog an2 14 23 j2 i analog an3 13 22 j1 i analog an4 12 21 h2 i analog an5 11 20 h1 i analog an6 17 26 l1 i analog an7 18 27 j3 i analog an8 21 32 k4 i analog an9 22 33 l4 i analog an10 23 34 l5 i analog an11 24 35 j5 i analog an12 27 41 j7 i analog an13 28 42 l7 i analog an14 29 43 k7 i analog an15 30 44 l8 i analog clki 39 63 f9 i st/cmos external clock source input. always associated with osc1 pin function. clko 40 64 f11 o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 39 63 f9 i st/cmos oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. osc2 40 64 f11 i/o ? oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci 47 73 c10 i st/cmos 32.768 khz low-power oscillator crystal input; cmos otherwise. sosco 48 74 b11 o ? 32.768 khz low-power oscillator crystal output. legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 33 pic32mx5xx/6xx/7xx cn0 48 74 b11 i st change notification inputs. can be software programmed for internal weak pull-ups on all inputs. cn1 47 73 c10 i st cn2 16 25 k2 i st cn3 15 24 k1 i st cn4 14 23 j2 i st cn5 13 22 j1 i st cn6 12 21 h2 i st cn7 11 20 h1 i st cn8 4 10 e3 i st cn9 5 11 f4 i st cn10 6 12 f2 i st cn11 8 14 f3 i st cn12 30 44 l8 i st cn13 52 81 c8 i st cn14 53 82 b8 i st cn15 54 83 d7 i st cn16 55 84 c7 i st cn17 31 49 l10 i st cn18 32 50 l11 i st cn19 ? 80 d8 i st cn20 ? 47 l9 i st cn21 ? 48 k9 i st ic1 42 68 e9 i st capture inputs 1-5 ic2 43 69 e10 i st ic3 44 70 d11 i st ic4 45 71 c11 i st ic5 52 79 a9 i st ocfa 17 26 l1 i st output compare fault a input oc1 46 72 d9 o ? output compare output 1 oc2 49 76 a11 o ? output compare output 2 oc3 50 77 a10 o ? output compare output 3 oc4 51 78 b9 o ? output compare output 4 oc5 52 81 c8 o ? output compare output 5 ocfb 30 44 l8 i st output compare fault b input int0 46 72 d9 i st external interrupt 0 int1 42 18 g1 i st external interrupt 1 int2 43 19 g2 i st external interrupt 2 int3 44 66 e11 i st external interrupt 3 int4 45 67 e8 i st external interrupt 4 table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 34 ? 2009-2011 microchip technology inc. ra0 ? 17 g3 i/o st porta is a bidirectional i/o port ra1 ? 38 j6 i/o st ra2 ? 58 h11 i/o st ra3 ? 59 g10 i/o st ra4 ? 60 g11 i/o st ra5 ? 61 g9 i/o st ra6 ? 91 c5 i/o st ra7 ? 92 b5 i/o st ra9 ? 28 l2 i/o st ra10 ? 29 k3 i/o st ra14 ? 66 e11 i/o st ra15 ? 67 e8 i/o st rb0 16 25 k2 i/o st portb is a bidirectional i/o port rb1 15 24 k1 i/o st rb2 14 23 j2 i/o st rb3 13 22 j1 i/o st rb4 12 21 h2 i/o st rb5 11 20 h1 i/o st rb6 17 26 l1 i/o st rb7 18 27 j3 i/o st rb8 21 32 k4 i/o st rb9 22 33 l4 i/o st rb10 23 34 l5 i/o st rb11 24 35 j5 i/o st rb12 27 41 j7 i/o st rb13 28 42 l7 i/o st rb14 29 43 k7 i/o st rb15 30 44 l8 i/o st rc1 ? 6 d1 i/o st portc is a bidirectional i/o port rc2 ? 7 e4 i/o st rc3 ? 8 e2 i/o st rc4 ? 9 e1 i/o st rc12 39 63 f9 i/o st rc13 47 73 c10 i/o st rc14 48 74 b11 i/o st rc15 40 64 f11 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 35 pic32mx5xx/6xx/7xx rd0 46 72 d9 i/o st portd is a bidirectional i/o port rd1 49 76 a11 i/o st rd2 50 77 a10 i/o st rd3 51 78 b9 i/o st rd4 52 81 c8 i/o st rd5 53 82 b8 i/o st rd6 54 83 d7 i/o st rd7 55 84 c7 i/o st rd8 42 68 e9 i/o st rd9 43 69 e10 i/o st rd10 44 70 d11 i/o st rd11 45 71 c11 i/o st rd12 ? 79 a9 i/o st rd13 ? 80 d8 i/o st rd14 ? 47 l9 i/o st rd15 ? 48 k9 i/o st re0 60 93 a4 i/o st porte is a bidirectional i/o port re1 61 94 b4 i/o st re2 62 98 b3 i/o st re3 63 99 a2 i/o st re4 64 100 a1 i/o st re5 1 3 d3 i/o st re6 2 4 c1 i/o st re7 3 5 d2 i/o st re8 ? 18 g1 i/o st re9 ? 19 g2 i/o st rf0 58 87 b6 i/o st portf is a bidirectional i/o port rf1 59 88 a6 i/o st rf2 ? 52 k11 i/o st rf3 33 51 k10 i/o st rf4 31 49 l10 i/o st rf5 32 50 l11 i/o st rf8 ? 53 j10 i/o st rf12 ? 40 k6 i/o st rf13 ? 39 l6 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 36 ? 2009-2011 microchip technology inc. rg0 ? 90 a5 i/o st portg is a bidirectional i/o port rg1 ? 89 e6 i/o st rg6 4 10 e3 i/o st rg7 5 11 f4 i/o st rg8 6 12 f2 i/o st rg9 8 14 f3 i/o st rg12 ? 96 c3 i/o st rg13 ? 97 a3 i/o st rg14 ? 95 c4 i/o st rg15 ? 1 b2 i/o st rg2 37 57 h10 i st portg input pins rg3 36 56 j11 i st t1ck 48 74 b11 i st timer1 external clock input t2ck ? 6 d1 i st timer2 external clock input t3ck ? 7 e4 i st timer3 external clock input t4ck ? 8 e2 i st timer4 external clock input t5ck ? 9 e1 i st timer5 external clock input u1cts 43 47 l9 i st uart1 clear to send u1rts 49 48 k9 o ? uart1 ready to send u1rx 50 52 k11 i st uart1 receive u1tx 51 53 j10 o ? uart1 transmit u3cts 8 14 f3 i st uart3 clear to send u3rts 4 10 e3 o ? uart3 ready to send u3rx 511f4 i st uart3 receive u3tx 612f2 o ? uart3 transmit u2cts 21 40 k6 i st uart2 clear to send u2rts 29 39 l6 o ? uart2 ready to send u2rx 31 49 l10 i st uart2 receive u2tx 32 50 l11 o ? uart2 transmit u4rx 43 47 l9 i st uart4 receive u4tx 49 48 k9 o ? uart4 transmit u6rx 814f3 i st uart6 receive u6tx 410e3 o ? uart6 transmit u5rx 21 40 k6 i st uart5 receive u5tx 29 39 l6 o ? uart5 transmit sck1 ? 70 d11 i/o st synchronous serial clock input/output for spi1 sdi1 ? 9 e1 i st spi1 data in sdo1 ? 72 d9 o ? spi1 data out table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 37 pic32mx5xx/6xx/7xx s s1 ? 69 e10 i/o st spi1 slave synchronization or frame pulse i/o sck3 49 48 k9 i/o st synchronous serial clock input/output for spi3 sdi3 50 52 k11 i st spi3 data in sdo3 51 53 j10 o ? spi3 data out ss3 43 47 l9 i/o st spi3 slave synchronization or frame pulse i/o sck2 4 10 e3 i/o st synchronous serial clock input/output for spi2 sdi2 5 11 f4 i st spi2 data in sdo2 6 12 f2 o ? spi2 data out ss2 8 14 f3 i/o st spi2 slave synchronization or frame pulse i/o sck4 29 39 l6 i/o st synchronous serial clock input/output for spi4 sdi4 31 49 l10 i st spi4 data in sdo4 32 50 l11 o ? spi4 data out ss4 21 40 k6 i/o st spi4 slave synchronization or frame pulse i/o scl1 44 66 e11 i/o st synchronous serial clock input/output for i2c1 sda1 43 67 e8 i/o st synchronous serial data input/output for i2c1 scl3 51 53 j10 i/o st synchronous serial clock input/output for i2c3 sda3 50 52 k11 i/o st synchronous serial data input/output for i2c3 scl2 ? 58 h11 i/o st synchronous serial clock input/output for i2c2 sda2 ? 59 g10 i/o st synchronous serial data input/output for i2c2 scl4 6 12 f2 i/o st synchronous serial clock input/output for i2c4 sda4 5 11 f4 i/o st synchronous serial data input/output for i2c4 scl5 32 50 l11 i/o st synchronous serial clock input/output for i2c5 sda5 31 49 l10 i/o st synchronous serial data input/output for i2c5 tms 23 17 g3 i st jtag test mode select pin tck 27 38 j6 i st jtag test clock input pin tdi 28 60 g11 i st jtag test data input pin tdo 24 61 g9 o ? jtag test data output pin rtcc 42 68 e9 o ? real-time clock alarm output cv ref - 15 28 l2 i analog comparator voltage reference (low) cv ref + 16 29 k3 i analog comparator voltage reference (high) cv refout 23 34 l5 o analog comparator voltage reference output c1in- 12 21 h2 i analog comparator 1 negative input c1in+ 11 20 h1 i analog comparator 1 positive input c1out 21 32 k4 o ? comparator 1 output c2in- 14 23 j2 i analog comparator 2 negative input c2in+ 13 22 j1 i analog comparator 2 positive input c2out 22 33 l4 o ? comparator 2 output table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 38 ? 2009-2011 microchip technology inc. pma0 30 44 l8 i/o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 k7 i/o ttl/st parallel master port address bit 1 input (buffered slave modes) and output (master modes) pma2 8 14 f3 o ? parallel master port address (demultiplexed master modes) pma3 6 12 f2 o ? pma4 5 11 f4 o ? pma5 4 10 e3 o ? pma6 16 29 k3 o ? pma7 22 28 l2 o ? pma8 32 50 l11 o ? pma9 31 49 l10 o ? pma10 28 42 l7 o ? pma11 27 41 j7 o ? pma12 24 35 j5 o ? pma13 23 34 l5 o ? pma14 45 71 c11 o ? pma15 44 70 d11 o ? pmcs1 45 71 c11 o ? parallel master port chip select 1 strobe pmcs2 44 70 d11 o ? parallel master port chip select 2 strobe pmd0 60 93 a4 i/o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd1 61 94 b4 i/o ttl/st pmd2 62 98 b3 i/o ttl/st pmd3 63 99 a2 i/o ttl/st pmd4 64 100 a1 i/o ttl/st pmd5 1 3 d3 i/o ttl/st pmd6 2 4 c1 i/o ttl/st pmd7 3 5 d2 i/o ttl/st pmd8 ? 90 a5 i/o ttl/st pmd9 ? 89 e6 i/o ttl/st pmd10 ? 88 a6 i/o ttl/st pmd11 ? 87 b6 i/o ttl/st pmd12 ? 79 a9 i/o ttl/st pmd13 ? 80 d8 i/o ttl/st pmd14 ? 83 d7 i/o ttl/st pmd15 ? 84 c7 i/o ttl/st table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 39 pic32mx5xx/6xx/7xx pmall 30 44 l8 o ? parallel master port address latch enable low byte (multiplexed master modes) pmalh 29 43 k7 o ? parallel master port address latch enable high byte (multiplexed master modes) pmrd 53 82 b8 o ? parallel master port read strobe pmwr 52 81 c8 o ? parallel master port write strobe v bus 34 54 h8 i analog usb bus power monitor v usb 35 55 h9 p ? usb internal transceiver supply. if the usb module is not used, this pin must be connected to v dd . v buson 11 20 h1 o ? usb host and otg bus power control output d+ 37 57 h10 i/o analog usb d+ d- 36 56 j11 i/o analog usb d- usbid 33 51 k10 i st usb otg id detect c1rx 58 87 b6 i st can1 bus receive pin c1tx 59 88 a6 o ? can1 bus transmit pin ac1rx 32 40 k6 i st alternate can1 bus receive pin ac1tx 31 39 l6 o ? alternate can1 bus transmit pin c2rx 29 90 a5 i st can2 bus receive pin c2tx 21 89 e6 o ? can2 bus transmit pin ac2rx ? 8 e2 1 st alternate can2 bus receive pin ac2tx ? 7 e4 o ? alternate can2 bus transmit pin erxd0 61 41 j7 i st ethernet receive data 0 (2) erxd1 60 42 l7 i st ethernet receive data 1 (2) erxd2 59 43 k7 i st ethernet receive data 2 (2) erxd3 58 44 l8 i st ethernet receive data 3 (2) erxerr 64 35 j5 i st ethernet receive error input (2) erxdv 62 12 f2 i st ethernet receive data valid (2) ecrsdv 62 12 f2 i st ethernet carrier sense data valid (2) erxclk 63 14 f3 i st ethernet receive clock (2) erefclk 63 14 f3 i st ethernet reference clock (2) etxd0 2 88 a6 o ? ethernet transmit data 0 (2) etxd1 3 87 b6 o ? ethernet transmit data 1 (2) etxd2 43 79 a9 o ? ethernet transmit data 2 (2) etxd3 42 80 d8 o ? ethernet transmit data 3 (2) etxerr 54 89 e6 o ? ethernet transmit error (2) etxen 1 83 d7 o ? ethernet transmit enable (2) etxclk 55 84 c7 i st ethernet transmit clock (2) ecol 44 10 e3 i st ethernet collision detect (2) ecrs 45 11 f4 i st ethernet carrier sense (2) table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 40 ? 2009-2011 microchip technology inc. emdc 30 71 c11 o ? ethernet management data clock (2) emdio 49 68 e9 i/o ? ethernet management data (2) aerxd0 43 18 g1 i st alternate ethernet receive data 0 (2) aerxd1 42 19 g2 i st alternate ethernet receive data 1 (2) aerxd2 ? 28 l2 i st alternate ethernet receive data 2 (2) aerxd3 ? 29 k3 i st alternate ethernet receive data 3 (2) aerxerr 55 1 b2 i st alternate ethernet receive error input (2) aerxdv ? 12 f2 i st alternate ethernet receive data valid (2) aecrsdv 44 12 f2 i st alternate ethernet carrier sense data valid (2) aerxclk ? 14 f3 i st alternate ethernet receive clock (2) aerefclk 45 14 f3 i st alternate ethernet reference clock (2) aetxd0 59 47 l9 o ? alternate ethernet transmit data 0 (2) aetxd1 58 48 k9 o ? alternate ethernet transmit data 1 (2) aetxd2 ? 44 l8 o ? alternate ethernet transmit data 2 (2) aetxd3 ? 43 k7 o ? alternate ethe rnet transmit data 3 (2) aetxerr ? 35 j5 o ? alternate ethernet transmit error (2) aetxen 54 67 e8 o ? alternate ethernet transmit enable (2) aetxclk ? 66 e11 i st alternate ethernet transmit clock (2) aecol ? 42 l7 i st alternate ethernet collision detect (2) aecrs ? 41 j7 i st alternate ethernet carrier sense (2) aemdc 30 71 c11 o ? alternate ether net management data clock (2) aemdio 49 68 e9 i/o ? alternate ethernet management data (2) trclk ? 91 c5 o ? trace clock trd0 ? 97 a3 o ? trace data bits 0-3 trd1 ? 96 c3 o ? trd2 ? 95 c4 o ? trd3 ? 92 b5 o ? pged1 16 25 k2 i/o st data i/o pin for programming/debugging communication channel 1 pgec1 15 24 k1 i st clock input pin for programming/debugging communication channel 1 pged2 18 27 j3 i/o st data i/o pin for programming/debugging communication channel 2 pgec2 17 26 l1 i st clock input pin for programming/debugging communication channel 2 mclr 7 13 f1 i/p st master clear (reset) input. this pin is an active-low reset to the device. table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 41 pic32mx5xx/6xx/7xx av dd 19 30 j4 p p positive supply for analog modules. this pin must be connected at all times. av ss 20 31 l3 p p ground reference for analog modules v dd 10, 26, 38, 57 2, 16, 37, 46, 62, 86 a7, c2, c9, e5, k8, f8, g5, h4, h6 p ? positive supply for peripheral logic and i/o pins v cap /v core 56 85 b7 p ? capacitor for internal voltage regulator v ss 9, 25, 41 15, 36, 45, 65, 75 a8, b10, d4, d5, e7, f5, f10, g6, g7, h3 p ? ground reference for logic and i/o pins. this pin must be connected at all times. v ref + 16 29 k3 i analog analog voltage reference (high) input v ref - 15 28 l2 i analog analog voltage reference (low) input table 1-1: pinout i/o descriptions (continued) pin name pin number (1) pin type buffer type description 64-pin qfn/tqfp 100-pin tqfp 121-pin xbga legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer note 1: pin numbers are provided for reference only. see the ? pin diagrams ? section for device pin availability. 2: see section 24.0 ?ethernet controller? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 42 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 43 pic32mx5xx/6xx/7xx 2.0 guidelines for getting started with 32-bit microcontrollers 2.1 basic connection requirements getting started with the pic32mx5xx/6xx/7xx family of 32-bit microcontrollers (mcus) requires attention to a minimal set of device pin connections before pro- ceeding with development. the following is a list of pin names, which must always be connected: ? all v dd and v ss pins (see section 2.2 ?decoupling capacitors? ) ? all av dd and av ss pins even if the adc module is not used (see section 2.2 ?decoupling capacitors? ) ?v cap /v core pin (see section 2.3 ?capacitor on internal voltage regulator (v cap /v core )? ) ?mclr pin (see section 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins when external oscillator source is used (see section 2.8 ?externa l oscillator pins? ) the following pin may be required, as well: v ref +/v ref - pins used when external voltage reference for adc module is implemented 2.2 decoupling capacitors the use of decoupling capacitors on power supply pins, such as v dd , v ss , av dd and av ss is required. see figure 2-1 . consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a value of 0.1 f (100 nf), 10-20v is recommended. the capacitor should be a low equivalent series resistance (low-esr) capacitor and have resonance fre- quency in the range of 20 mhz and higher. it is further recommended to use ceramic capacitors. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended that the capacitors be placed on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb track inductance. note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the av dd and av ss pins must be connected, regardless of the adc use and the adc voltage reference source. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 44 ? 2009-2011 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 bulk capacitors the use of a bulk capacitor is recommended to improve power supply stability. typical values range from 4.7 f to 47 f. this capacitor sh ould be located as close to the device as possible. 2.3 capacitor on internal voltage regulator (v cap /v core ) 2.3.1 internal regulator mode a low-esr (1 ohm) capacitor is required on the v cap /v core pin, which is used to stabilize the internal voltage regulator output. the v cap /v core pin must not be connected to v dd , and must have a c efc capaci- tor, with at least a 6v rati ng, connected to ground. the type can be ceramic or tantalum. refer to section 31.0 ?electrical characteristics? for additional information on c efc specifications. 2.4 master clear (mclr ) pin the mclr pin provides two specific device functions: ? device reset ? device programming and debugging pulling the mclr pin low generates a device reset. figure 2-2 illustrates a typical mclr circuit. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as illustrated in figure 2-2 , it is recommended that the capaci tor c, be isolated from the mclr pin during programming and debugging operations. place the components illustrated in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections pic32 v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c r v dd mclr 0.1 f ceramic v cap /v core 10 r1 c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp 0.1 f ceramic c bp c efc note 1: r 10 k is recommended. a suggested start- ing value is 10 k . ensure that the mclr pin v ih and v il specifications are met. 2: r1 470 will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. 3: the capacitor can be sized to prevent uninten- tional resets from brief glitches or to extend the device reset period during the por. c r1 r v dd mclr pic32 jp free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 45 pic32mx5xx/6xx/7xx 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? icd 2, mplab ? icd 3 or mplab ? real ice?. for more information on icd 2, icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. ? ?mplab ? icd 2 in-circuit debugger user?s guide? ds51331 ? ?using mplab ? icd 2? (poster) ds51265 ? ?mplab ? icd 2 design advisory? ds51566 ? ?using mplab ? icd 3? (poster) ds51765 ? ?mplab ? icd 3 design advisory? ds51764 ? ?mplab ? real ice? in-circuit emulator user?s guide? ds51616 ? ?using mplab ? real ice? emulator? (poster) ds51749 2.6 jtag the tms, tdo, tdi and tck pins are used for testing and debugging according to the joint test action group (jtag) standard. it is recommended to keep the trace length between the jtag connector and the jtag pins on the device as short as possible. if the jtag connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the tms, tdo, tdi and tck pins are not recommended as they will interfere with the programmer/debugger communications to the device. if such discrete compo- nents are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to the ac/dc character- istics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. 2.7 trace the trace pins can be connected to a hardware-trace- enabled programmer to provide a compress real time instruction trace. when us ed for trace the trd3, trd2, trd1, trd0 and trclk pins should be dedicated for this use. the trace hardware requires a22 series resistor between the trace pins and the trace connector. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 46 ? 2009-2011 microchip technology inc. 2.8 external oscillator pins many mcus have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. refer to section 8.0 ?oscillator configuration? for details. the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator cir- cuit close to the respective oscillator pins, not exceed- ing one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscilla tor circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or po wer traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the boa rd where the crystal is placed. a suggested layout is illustrated in figure 2-3 . figure 2-3: suggested oscillator circuit placement 2.9 configuration of analog and digital pins during icsp operations if mplab icd 2, icd 3 or real ice is selected as a debugger, it automatically initializes all of the analog-to-digital input pins (anx) as ?digital? pins by setting all bits in the adpcfg register. the bits in this register that correspond to the analog- to-digital pins that are init ialized by mplab icd 2, icd 3 or real ice, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain adc pins as analog input pins during the debug session, the user application must clear the corresponding bits in the adpcfg register during initialization of the adc module. when mplab icd 2, icd 3 or real ice is used as a programmer, the user application firmware must cor- rectly configure the adpcfg register. automatic initial- ization of this register is only done during debugger operation. failure to correct ly configure the register(s) will result in all adc pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.10 unused i/os unused i/o pins should not be allowed to float as inputs. they can be config ured as outputs and driven to a logic-low state. alternatively, inputs can be reserved by connecting the pin to v ss through a 1k to 10k resistor and configuring the pin as an input. main oscillator guard ring guard trace secondary oscillator free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 47 pic32mx5xx/6xx/7xx 2.11 referenced sources this device data sheet is based on the following individual chapters of the ?pic32 family reference manual? . these documents should be considered as the general reference for t he operation of a particular module or device feature. ? section 1. ?introduction? (ds61127) ? section 2. ?cpu? (ds61113) ? section 4. ?prefetch cache? (ds61119) ? section 3. ?memory organization? (ds61115) ? section 5. ?flash program memory? (ds61121) ? section 6. ?oscillator configuration? (ds61112) ? section 7. ?resets? (ds61118) ? section 8. ?interrupt controller? (ds61108) ? section 9. ?watchdog timer and power-up timer (ds61114) ? section 10. ?power-saving features? (ds61130) ? section 12. ?i/o ports? (ds61120) ? section 13. ?parallel master port (pmp)? (ds61128) ? section 14. ?timers? (ds61105) ? section 15. ?input capture? (ds61122) ? section 16. ?output capture? (ds61111) ? section 17. ?10-bit analog-to -digital converter (adc)? (ds61104) ? section 19. ?comparator? (ds61110) ? section 20. ?comparator voltage reference (cv ref )? (ds61109) ? section 21. ?universal asynchronous receiver transmitter (uart)? (ds61107) ? section 23. ?serial peri pheral interface (spi)? (ds61106) ? section 24. ?inter-integ rated circuit (i2c?)? (ds61116) ? section 27. ?usb on-the-go (otg)? (ds61126) ? section 29. ?real-time clock and calendar (rtcc)? (ds61125) ? section 31. ?direct memory access (dma) controller? (ds61117) ? section 32. ?configuration? (ds61124) ? section 33. ?programming and diagnostics? (ds61129) ? section 34. ?controller area network (can)? (ds61154) ? section 35. ?ethernet controller? (ds61155) note 1: to access the documents listed below, browse to the documentation section of the pic32mx795f512l product page on the microchip web site ( www.microchip.com ) or select a family reference manual section from the following list. in addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 48 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 49 pic32mx5xx/6xx/7xx 3.0 cpu the mips32 ? m4k ? processor core is the heart of the pic32mx5xx/6xx/7xx family processor. the cpu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. 3.1 features ? 5-stage pipeline ? 32-bit address and data paths ? mips32 enhanced architecture (release 2) - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions ? mips16e ? code compression - 16-bit encoding of 32-bit instructions to improve code density - special pc-relative instructions for efficient loading of addresses and constants - save and restore macro instructions for setting up and tearing down stack frames within subroutines - improved support for handling 8 and 16-bit data types ? simple fixed mapping translation (fmt) mechanism ? simple dual bus interface - independent 32-bit address and data busses - transactions can be aborted to improve interrupt latency ? autonomous multiply/divide unit - maximum issue rate of one 32x16 multiply per clock - maximum issue rate of one 32x32 multiply every other clock - early-in iterative divide. minimum 11 and maximum 33 clock latency (dividend ( rs ) sign extension-dependent) ? power control - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ? ejtag debug and instruction trace - support for single stepping - virtual instruction and data address/value - breakpoints - pc tracing with trace compression figure 3-1: mips ? m4k ? processor core block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds61113) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.micro- chip.com/pic32 ). resources for the mips32 ? m4k ? processor core are available at http://www.mips.com . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dual bus i/f system coprocessor mdu fmt tap ejtag power management off-chip debug i/f execution core (rf/alu/shift) bus matrix trace trace i/f bus interface cpu free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 50 ? 2009-2011 microchip technology inc. 3.2 architecture overview the mips ? m4k ? processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. the following blocks are in cluded with the core: ? execution unit ? multiply/divide unit (mdu) ? system control coprocessor (cp0) ? fixed mapping translation (fmt) ? dual internal bus interfaces ? power management ? mips16e support ? enhanced jtag (ejtag) controller 3.2.1 execution unit the mips m4k processor core execution unit imple- ments a load/store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autono- mous multiply/divide unit. the core contains thirty-two 32-bit general purpose registers (gprs) used for integer operations and address calculation. one addi- tional register file shadow set (containing thirty-two reg- isters) is added to minimize context switching overhead during interrupt/exception proc essing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: ? 32-bit adder used for calculating the data address ? address unit for calculating the next instruction address ? logic for branch determination and branch target address calculation ? load aligner ? bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results ? leading zero/one detect unit for implementing the clz and clo instructions ? arithmetic logic unit (alu) for performing bitwise logical operations ? shifter and store aligner 3.2.2 multiply/divide unit (mdu) mips m4k processor core includes a multiply/divide unit (mdu) that contains a separate pipeline for multi- ply and divide operations. this pipeline operates in par- allel with the integer unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows mdu opera- tions to be partially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x16 booth recoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the pic32 core only checks t he value of the latter ( rt) operand to determine how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass through the multiplier once. a 32x32 operation passes through the multiplier twice. the mdu supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. the multiply operand size is automatically determined by logic built into the mdu. divide operations are implemented with a simple 1 bit per clock iterative algorith m. an early-in detection checks the sign extension of the dividend ( rs ) operand. if rs is 8 bits wide, 23 iterations are skipped. for a 16 bit wide rs , 15 iterations are skipped and for a 24 bit wide rs , 7 iterations are skipped. any attempt to issue a subsequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation is completed. table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num- ber of cycles until a result is available) for the pic32 core multiply and divide instructions. the approximate latency and repeat rates are listed in terms of pipeline clocks. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 51 pic32mx5xx/6xx/7xx table 3-1: mips ? m4k ? core high-performance integer multiply/divide unit latencies and repeat rates the mips architecture defines that the result of a multiply or divide operation be placed in the hi and lo registers. using the move-from-hi ( mfhi ) and move- from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 architecture also defines a multiply instruction, mul , which places the least significant results in the pri- mary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction required when using the lo register, and by supporting multiple desti- nation registers, the throug hput of multiply-intensive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtra cts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. 3.2.3 system control coprocessor (cp0) in the mips architecture, cp0 is responsible for the virtual-to-physical address translation, the exception control system, the processor?s diagnostics capability, the operating modes (kernel, user and debug) and whether interrupts are enabled or disabled. configura- tion information, such as presence of options like mips16e, is also available by accessing the cp0 registers, listed in ta b l e 3 - 2 . opcode operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu 16 bits 1 1 32 bits 2 2 mul 16 bits 2 1 32 bits 3 2 div/divu 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 52 ? 2009-2011 microchip technology inc. table 3-2: coprocessor 0 registers register number register name function 0-6 reserved reserved. 7 hwrena enables access via the rdhwr instruction to select ed hardware registers. 8 badvaddr (1) reports the address for the most recent address-related exception. 9 count (1) processor cycle count. 10 reserved reserved. 11 compare (1) timer interrupt control. 12 status (1) processor status and control. 12 intctl (1) interrupt system status and control. 12 srsctl (1) shadow register set status and control. 12 srsmap (1) provides mapping from vectored interrupt to a shadow set. 13 cause (1) cause of last general exception. 14 epc (1) program counter at last exception. 15 prid processor identification and revision. 15 ebase exception vector base register. 16 config configuration register. 16 config1 configuration register 1. 16 config2 configuration register 2. 16 config3 configuration register 3. 17-22 reserved reserved. 23 debug (2) debug control and exception status. 24 depc (2) program counter at last debug exception. 25-29 reserved reserved. 30 errorepc (1) program counter at last error. 31 desave (2) debug handler scratchpad register. note 1: registers used in exception processing. 2: registers used during debug. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 53 pic32mx5xx/6xx/7xx coprocessor 0 also contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. table 3-3 lists the exception types in order of priority. table 3-3: pic32mx5xx/6xx/7xx family core exception types exception description reset assertion mclr or a power-on reset (por). dss ejtag debug single step. dint ejtag debug interrupt. caused by the assertion of the external ej_dint input or by setting the ejtagbrk bit in the ecr register. nmi assertion of nmi signal. interrupt assertion of unmasked hardware or software interrupt signal. dib ejtag debug hardware instruction break matched. adel fetch address alignment error. fetch reference to protected address. ibe instruction fetch bus error. dbp ejtag breakpoint (execution of sdbbp instruction). sys execution of syscall instruction. bp execution of break instruction. ri execution of a reserved instruction. cpu execution of a coprocessor instruction for a coprocessor that is not enabled. ceu execution of a corextend instruction when corextend is not enabled. ov execution of an arithmetic instruction that overflowed. tr execution of a trap (when trap condition is true). ddbl/ddbs ejtag data address break (address only) or ejtag data value break on store (address + value). adel load address alignment error. load reference to protected address. ades store address alignment error. store to protected address. dbe load or store bus error. ddbl ejtag data hardware breakpoint matched in load data compare. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 54 ? 2009-2011 microchip technology inc. 3.3 power management the mips m4k processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumpti on during idle periods. 3.3.1 instruction-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 27.0 ?power-saving features? . 3.3.2 local clock gating the majority of the power consumed by the pic32mx5xx/6xx/7xx family co re is in the clock tree and clocking registers. the pic32 family uses exten- sive use of local gated clocks to reduce this dynamic power consumption. 3.4 ejtag debug support the mips m4k processor core provides for an enhanced jtag (ejtag) interf ace for use in the soft- ware debug of application and kernel code. in addition to standard user mode and kernel modes of operation, the mips m4k core prov ides a debug mode that is entered after a debug exception (derived from a hard- ware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. duri ng this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for trans- ferring test data in and out of the mips m4k processor core. in addition to the standard jtag instructions, special instructions defined in the ejtag specification define which registers are selected and how they are used. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 55 pic32mx5xx/6xx/7xx 4.0 memory organization pic32mx5xx/6xx/7xx microcontrollers provide 4 gb of unified virtual memory address space. all memory regions, including program, data memory, sfrs and configuration registers, reside in this address space at their respective unique addresses. the program and data memories can be optionally partitioned into user and kernel memories. in addition, the data memory can be made executable, allowing pic32mx5xx/6xx/7xx devices to execute from data memory. key features include: ? 32-bit native data width ? separate user (kuseg) and kernel (kseg0/kseg1) mode address space ? flexible program flash memory partitioning ? flexible data ram partitioning for data and program space ? separate boot flash memory for protected code ? robust bus exception handling to intercept runaway code ? simple memory mapping with fixed mapping translation (fmt) unit ? cacheable (kseg0) and non-cacheable (kseg1) address regions 4.1 pic32mx5xx/6xx/7xx memory layout pic32mx5xx/6xx/7xx microcontrollers implement two address schemes: virtual and physical. all hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. virtual addresses are exclusively used by the cpu to fetch and execute instructions as well as access peripheral s. physical addresses are used by bus master peripherals, such as dma and the flash controller, that access memory independently of the cpu. the memory maps for the pic32mx5xx/6xx/7xx devices are illustrated in figure 4-1 through figure 4-6 . 4.1.1 peripheral registers locations table 4-1 through ta b l e 4 - 4 4 contain the peripheral address maps for the pic32mx5xx/6xx/7xx devices. peripherals loca ted on the pb bus are mapped to 512-byte boundaries. peripherals on the fpb bus are mapped to 4-kbyte boundaries. note: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. for detailed information, refer to section 3. ?memory organization? (ds61115) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 56 ? 2009-2011 microchip technology inc. figure 4-1: memory map on reset fo r PIC32MX564F064H, pic32mx564f064l, pic32mx664f064h and pic32mx664f064l devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 57 pic32mx5xx/6xx/7xx figure 4-2: memory map on reset for pic32mx534f064h an d pic32mx534f064l devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0004000 0xa0003fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80004000 0x80003fff ram (2) 0x1d000000 reserved 0x80000000 0x00004000 reserved ram (2) 0x00003fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 58 ? 2009-2011 microchip technology inc. figure 4-3: memory map on reset fo r pic32mx564f128h, pic32mx564f128l, pic32mx664f128h, pi c32mx664f128l, pi c32mx764f128h and pic32mx764f128l devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd020000 0xbd01ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d020000 0x1f800000 0x9d01ffff program flash (2) reserved 0x9d000000 0x1d020000 reserved program flash (2) 0x1d01ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 59 pic32mx5xx/6xx/7xx figure 4-4: memory map on reset fo r pic32mx575f256h, pic32mx575f256l, pic32mx675f256h, pi c32mx675f256l, pic32mx775f256h and pic32mx775f256l devices (1) virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd040000 0xbd03ffff program flash (2) 0xbd000000 reserved 0xa0010000 0xa000ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d040000 0x1f800000 0x9d03ffff program flash (2) reserved 0x9d000000 0x1d040000 reserved program flash (2) 0x1d03ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00010000 reserved ram (2) 0x0000ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 60 ? 2009-2011 microchip technology inc. figure 4-5: memory map on reset fo r pic32mx575f512h, pic32mx575f512l, pic32mx675f512h, pi c32mx675f512l, pi c32mx775f512h and pic32mx775f512l devices virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd080000 0xbd07ffff program flash (2) 0xbd000000 reserved 0xa0010000 0xa000ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d080000 0x1f800000 0x9d07ffff program flash (2) reserved 0x9d000000 0x1d080000 reserved program flash (2) 0x1d07ffff 0x80010000 0x8000ffff ram (2) 0x1d000000 reserved 0x80000000 0x00010000 reserved ram (2) 0x0000ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initializati on code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 61 pic32mx5xx/6xx/7xx figure 4-6: memory map on reset fo r pic32mx695f512h, pic32mx695f512l, pic32mx795f512h and pic32mx795f512l devices virtual memory map physical memory map 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd080000 0xbd07ffff program flash (2) 0xbd000000 reserved 0xa0020000 0xa001ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d080000 0x1f800000 0x9d07ffff program flash (2) reserved 0x9d000000 0x1d080000 reserved program flash (2) 0x1d07ffff 0x80020000 0x8001ffff ram (2) 0x1d000000 reserved 0x80000000 0x00020000 reserved ram (2) 0x0001ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds61115)) and can be changed by initializati on code provided by end user development tools (refer to the specific development tool documentation for information). kseg1 kseg0 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 62 ? 2009-2011 microchip technology inc. table 4-1: bus matrix register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 bmxcon (1) 31:16 ? ? ? ? ? bmxchedma ? ? ? ? ? bmxerrixi bmxerricd bmxerrdma bmxerrds bmxerris 001f 15:0 ? ? ? ? ? ? ? ? ?bmxwsdrm ? ? ? bmxarb<2:0> 0041 2010 bmxdkpba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdkpba<15:0> 0000 2020 bmxdudba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdudba<15:0> 0000 2030 bmxdupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdupba<15:0> 0000 2040 bmxdrmsz 31:16 bmxdrmsz<31:0> xxxx 15:0 xxxx 2050 bmxpupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? bmxpupba<19:16> 0000 15:0 bmxpupba<15:0> 0000 2060 bmxpfmsz 31:16 bmxpfmsz<31:0> xxxx 15:0 xxxx 2070 bmxbootsz 31:16 bmxbootsz<31:0> 0000 15:0 3000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 63 pic32mx5xx/6xx/7xx table 4-2: interrupt register map for pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h and pic32mx575f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/ 8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ?frz ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2 if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ? ? can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2 ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ? ? can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have correspond ing clr, set and inv registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564/664/764 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 64 ? 2009-2011 microchip technology inc. 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ? ? ? ? ? 0000 table 4-2: interrupt register map for pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h and pic32mx575f512h devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/ 8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have correspond ing clr, set and inv registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564/664/764 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 65 pic32mx5xx/6xx/7xx table 4-3: interrupt register map for pic32mx664f064h, pic32mx664f128h, pic32mx675f256h, pic32mx675f512h and pic32mx695f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ?frz ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif ? ? usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie ? ? usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 66 ? 2009-2011 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-3: interrupt register map for pic32mx664f064h, pic32mx664f128h, pic32mx675f256h, pic32mx675f512h and pic32mx695f512h devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 67 pic32mx5xx/6xx/7xx table 4-4: interrupt register map for pic32mx 764f128h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ss0 0000 15:0 ?frz ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif ? ? ? oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif can2if (2) can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif ? ? ? u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie ? ? ? oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie can2ie (2) can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie ? ? ? u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128h device. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 68 ? 2009-2011 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? ? ? ? ? ? ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? can2ip<2:0> (2) can2is<1:0> (2) ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-4: interrupt register map for pic32mx 764f128h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128h device. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 69 pic32mx5xx/6xx/7xx table 4-5: interrupt register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l pic32mx575f512l and pic32mx575f256l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ?frz ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ? ? can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ? ? can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 70 ? 2009-2011 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ? ? ? ? ? 0000 table 4-5: interrupt register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l pic32mx575f512l and pic32mx575f256l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx534/564 devices. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 71 pic32mx5xx/6xx/7xx table 4-6: interrupt register map fo r pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ?frz ? mvec ? tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif ? ? usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie ? ? usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does note have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 72 ? 2009-2011 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-6: interrupt register map fo r pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx664 devices. 3: this register does note have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 73 pic32mx5xx/6xx/7xx table 4-7: interrupt register map for pic32mx 764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ?frz ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif oc5if ic5if t5if int4if oc4if ic4if t4if 0000 31:16 spi3txif spi3rxif spi3eif i2c3mif i2c3sif i2c3bif 15:0 int3if oc3if ic3if t3if int2if oc2if ic2if t2if int1if oc1if ic1if t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 ic3eif ic2eif ic1eif ethif can2if (2) can1if usbif fceif dma7if (2) dma6if (2) dma5if (2) dma4if (2) dma3if dma2if dma1if dma0if 0000 rtccif fscmif i2c2mif i2c2sif i2c2bif u2txif u2rxif u2eif u3txif u3rxif u3eif cmp2if cmp1if pmpif ad1if cnif 0000 15:0 spi4txif spi4rxif spi4eif spi2txif spi2rxif spi2eif i2c5mif i2c5sif i2c5bif i2c4mif i2c4sif i2c4bif 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txif u5rxif u5eif u6txif u6rxif u6eif u4txif u4rxif u4eif pmpeif ic5eif ic4eif 0000 1060 iec0 i2c1mie i2c1sie i2c1bie u1txie u1rxie u1eie spi1txie spi1rxie spi1eie oc5ie ic5ie t5ie int4ie oc4ie ic4ie t4ie 0000 31:16 spi3txie spi3rxie spi3eie i2c3mie i2c3sie i2c3bie 15:0 int3ie oc3ie ic3ie t3ie int2ie oc2ie ic2ie t2ie int1ie oc1ie ic1ie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 ic3eie ic2eie ic1eie ethie can2ie (2) can1ie usbie fceie dma7ie (2) dma6ie (2) dma5ie (2) dma4ie (2) dma3ie dma2ie dma1ie dma0ie 0000 rtccie fscmie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie u3txie u3rxie u3eie cmp2ie cmp1ie pmpie ad1ie cnie 0000 15:0 spi4txie spi4rxie spi4eie spi2txie spi2rxie spi2eie i2c5mie i2c5sie i2c5bie i2c4mie i2c4sie i2c4bie 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? u5txie u5rxie u5eie u6txie u6rxie u6eie u4txie u4rxie u4eie pmpeie ic5eie ic4eie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128l device. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 74 ? 2009-2011 microchip technology inc. 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? spi1ip<2:0> spi1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 10f0 ipc6 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? cnip<2:0> cnis<1:0> 0000 ? ? ? i2c1ip<2:0> i2c1is<1:0> ? ? ? u1ip<2:0> u1is<1:0> 0000 15:0 spi3ip<2:0> spi3is<1:0> i2c3ip<2:0> i2c3is<1:0> 1100 ipc7 ? ? ? u3ip<2:0> u3is<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 31:16 spi2ip<2:0> spi2is<1:0> i2c4ip<2:0> i2c4is<1:0> 15:0 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 1110 ipc8 31:16 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 15:0 spi4ip<2:0> spi4is<1:0> i2c5ip<2:0> i2c5is<1:0> 1120 ipc9 31:16 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 15:0 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma7ip<2:0> (2) dma7is<1:0> (2) ? ? ? dma6ip<2:0> (2) dma6is<1:0> (2) 0000 15:0 ? ? ? dma5ip<2:0> (2) dma5is<1:0> (2) ? ? ? dma4ip<2:0> (2) dma4is<1:0> (2) 0000 1140 ipc11 31:16 ? ? ? can2ip<2:0> (2) can2is<1:0> (2) ? ? ? can1ip<2:0> can1is<1:0> 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 1150 ipc12 31:16 ? ? ? u5ip<2:0> u5is<1:0> ? ? ? u6ip<2:0> u6is<1:0> 0000 15:0 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? ethip<2:0> ethis<1:0> 0000 table 4-7: interrupt register map for pic32mx 764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: except where noted, all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this bit is unimplemented on pic32mx764f128l device. 3: this register does not have associated clr, set, and inv registers. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 75 pic32mx5xx/6xx/7xx table 4-8: timer1-timer5 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 t1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl twdis twip ? ? ?tgate ? tckps<1:0> ? tsync tcs ? 0000 0610 tmr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr1<15:0> 0000 0620 pr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr1<15:0> ffff 0800 t2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs (2) ? 0000 0810 tmr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr2<15:0> 0000 0820 pr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr2<15:0> ffff 0a00 t3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs (2) ? 0000 0a10 tmr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr3<15:0> 0000 0a20 pr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr3<15:0> ffff 0c00 t4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs (2) ? 0000 0c10 tmr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr4<15:0> 0000 0c20 pr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr4<15:0> ffff 0e00 t5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs (2) ? 0000 0e10 tmr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr5<15:0> 0000 0e20 pr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr5<15:0> ffff legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on 64-pin devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 76 ? 2009-2011 microchip technology inc. table 4-9: input capture 1-input capture 5 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ic1con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2010 ic1buf 31:16 ic1buf<31:0> xxxx 15:0 xxxx 2200 ic2con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2210 ic2buf 31:16 ic2buf<31:0> xxxx 15:0 xxxx 2400 ic3con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2410 ic3buf 31:16 ic3buf<31:0> xxxx 15:0 xxxx 2600 ic4con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2610 ic4buf 31:16 ic4buf<31:0> xxxx 15:0 xxxx 2800 ic5con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2810 ic5buf 31:16 ic5buf<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 77 pic32mx5xx/6xx/7xx table 4-10: output compare 1-output compare 5 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 oc1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3010 oc1r 31:16 oc1r<31:0> xxxx 15:0 xxxx 3020 oc1rs 31:16 oc1rs<31:0> xxxx 15:0 xxxx 3200 oc2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3210 oc2r 31:16 oc2r<31:0> xxxx 15:0 xxxx 3220 oc2rs 31:16 oc2rs<31:0> xxxx 15:0 xxxx 3400 oc3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3410 oc3r 31:16 oc3r<31:0> xxxx 15:0 xxxx 3420 oc3rs 31:16 15:0 oc3rs<31:0> xxxx xxxx 3600 oc4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3610 oc4r 31:16 oc4r<31:0> xxxx 15:0 xxxx 3620 oc4rs 31:16 15:0 oc4rs<31:0> xxxx xxxx 3800 oc5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3810 oc5r 31:16 oc5r<31:0> xxxx 15:0 xxxx 3820 oc5rs 31:16 oc5rs<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 78 ? 2009-2011 microchip technology inc. table 4-11: i2c1, i2c3, i2c4 and i2c5 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 i2c3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5010 i2c3stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5020 i2c5dd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5030 i2c3msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5040 i2c3brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5050 i2c3trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5060 i2c3rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5100 i2c4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5110 i2c4stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5120 i2c4add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5130 i2c4msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5140 i2c4brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5150 i2c4trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5160 i2c4rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5200 i2c5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5210 i2c5stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 79 pic32mx5xx/6xx/7xx 5220 i2c5add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5230 i2c5msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5240 i2c5brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5250 i2c5trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5260 i2c5rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5300 i2c1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5310 i2c1stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5320 i2c3dd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5330 i2c1msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5340 i2c1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5350 i2c1trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5360 i2c1rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 table 4-11: i2c1, i2c3, i2c4 and i2c5 register map (1) (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 80 ? 2009-2011 microchip technology inc. table 4-12: i2c2 register map for pic32mx534f064l, pic32mx564f064l, pi c32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5400 i2c2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 5410 i2c2stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a p s r/w rbf tbf 0000 5420 i2c4dd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? add<9:0> 0000 5430 i2c2msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? msk<9:0> 0000 5440 i2c2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5450 i2c2trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5460 i2c2rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 81 pic32mx5xx/6xx/7xx table 4-13: uart1 through uart6 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 u1mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6010 u1sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6020 u1txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6030 u1rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6040 u1brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6200 u4mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on frz sidl iren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6210 u4sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6220 u4txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6230 u4rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6240 u4brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6400 u3mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6410 u3sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6420 u3txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6430 u3rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6440 u3brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6600 u6mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl iren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6610 u6sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6620 u6txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 82 ? 2009-2011 microchip technology inc. 6630 u6rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6640 u6brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6800 u2mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl iren rtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6810 u2sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6820 u2txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6830 u2rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6840 u2brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 6a00 u5mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl iren ? ? ? ? wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6a10 u5sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 6a20 u5txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6a30 u5rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6a40 u5brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 brg<15:0> 0000 table 4-13: uart1 through uart6 register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 83 pic32mx5xx/6xx/7xx table 4-14: spi2, spi3 and spi4 register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 spi3con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on frz sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5810 spi3stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5820 spi3buf 31:16 data<31:0> 0000 15:0 0000 5830 spi3brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5a00 spi2con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on frz sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5a10 spi2stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5a20 spi2buf 31:16 data<31:0> 0000 15:0 0000 5a30 spi2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5c00 spi4con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on frz sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5c10 spi4stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ?spitbe ? spitbf spirbf 0008 5c20 spi4buf 31:16 data<31:0> 0000 15:0 0000 5c30 spi4brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 84 ? 2009-2011 microchip technology inc. table 4-15: spi1 register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5e00 spi1con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> ? ? ? ? ? ? spife enhbuf 0000 15:0 on frz sidl dissdo mode32 mode16 smp cke ssen ckp msten ? stxisel<1:0> srxisel<1:0> 0000 5e10 spi1stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? ? spibusy ? ? spitur srmt spirov spirbe ? spitbe ? spitbf spirbf 0008 5e20 spi1buf 31:16 data<31:0> 0000 15:0 0000 5e30 spi1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? brg<8:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 85 pic32mx5xx/6xx/7xx table 4-16: adc register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ad1con1 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? form<2:0> ssrc<2:0> clrasam ? asam samp done 0000 9010 ad1con2 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 vcfg2 vcfg1 vcfg0 offcal ?cscna ? ?bufs ? smpi<3:0> bufm alts 0000 9020 ad1con3 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 adrc ? ? samc<4:0> adcs<7:0> 0000 9040 ad1chs (1) 31:16 ch0nb ? ? ? ch0sb<3:0> ch0na ? ? ? ch0sa<3:0> 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 9060 ad1pcfg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pcfg15 pcfg14 pcfg13 pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 9050 ad1cssl (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 9070 adc1buf0 31:16 adc result word 0 (adc1buf0<31:0>) 0000 15:0 0000 9080 adc1buf1 31:16 adc result word 1 (adc1buf1<31:0>) 0000 15:0 0000 9090 adc1buf2 31:16 adc result word 2 (adc1buf2<31:0>) 0000 15:0 0000 90a0 adc1buf3 31:16 adc result word 3 (adc1buf3<31:0>) 0000 15:0 0000 90b0 adc1buf4 31:16 adc result word 4 (adc1buf4<31:0>) 0000 15:0 0000 90c0 adc1buf5 31:16 adc result word 5 (adc1buf5<31:0>) 0000 15:0 0000 90d0 adc1buf6 31:16 adc result word 6 (adc1buf6<31:0>) 0000 15:0 0000 90e0 adc1buf7 31:16 adc result word 7 (adc1buf7<31:0>) 0000 15:0 0000 90f0 adc1buf8 31:16 adc result word 8 (adc1buf8<31:0>) 0000 15:0 0000 9100 adc1buf9 31:16 adc result word 9 (adc1buf9<31:0>) 0000 15:0 0000 9110 adc1bufa 31:16 adc result word a (adc1bufa<31:0>) 0000 15:0 0000 9120 adc1bufb 31:16 adc result word b (adc1bufb<31:0>) 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 86 ? 2009-2011 microchip technology inc. 9130 adc1bufc 31:16 adc result word c (adc1bufc<31:0>) 0000 15:0 0000 9140 adc1bufd 31:16 adc result word d (adc1bufd<31:0>) 0000 15:0 0000 9150 adc1bufe 31:16 adc result word e (adc1bufe<31:0>) 0000 15:0 0000 9160 adc1buff 31:16 adc result word f (adc1buff<31:0>) 0000 15:0 0000 table 4-16: adc register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 87 pic32mx5xx/6xx/7xx table 4-17: dma global register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 dmacon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz ? suspend dmabusy ? ? ? ? ? ? ? ? ? ? ? 0000 3010 dmastat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rdwr dmach<2:0> (2) 0000 3020 dmaaddr 31:16 dmaaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dmach<3> bit is not available on pic32mx534/564/664/764 devices. table 4-18: dma crc register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 dcrccon 31:16 ? ? byto<1:0> wbo ? ? bito ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? plen<4:0> crcen crcapp crctyp ? ? crcch<2:0> 0000 3040 dcrcdata 31:16 dcrcdata<31:0> 0000 15:0 0000 3050 dcrcxor 31:16 dcrcxor<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 88 ? 2009-2011 microchip technology inc. table 4-19: dma channels 0-7 register map (1,2) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 dch0con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3070 dch0econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3080 dch0int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3090 dch0ssa 31:16 chssa<31:0> 0000 15:0 0000 30a0 dch0dsa 31:16 chdsa<31:0> 0000 15:0 0000 30b0 dch0ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 30c0 dch0dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 30d0 dch0sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 30e0 dch0dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 30f0 dch0csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3100 dch0cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3110 dch0dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3120 dch1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3130 dch1econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3140 dch1int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3150 dch1ssa 31:16 chssa<31:0> 0000 15:0 0000 3160 dch1dsa 31:16 chdsa<31:0> 0000 15:0 0000 3170 dch1ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 89 pic32mx5xx/6xx/7xx 3180 dch1dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3190 dch1sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 31a0 dch1dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 31b0 dch1csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 31c0 dch1cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 31d0 dch1dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 31e0 dch2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 31f0 dch2econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3200 dch2int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3210 dch2ssa 31:16 chssa<31:0> 0000 15:0 0000 3220 dch2dsa 31:16 chdsa<31:0> 0000 15:0 0000 3230 dch2ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3240 dch2dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3250 dch2sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3260 dch2dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3270 dch2csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3280 dch2cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 table 4-19: dma channels 0-7 register map (1,2) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 90 ? 2009-2011 microchip technology inc. 3290 dch2dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 32a0 dch3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 32b0 dch3econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 32c0 dch3int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 32d0 dch3ssa 31:16 chssa<31:0> 0000 15:0 0000 32e0 dch3dsa 31:16 chdsa<31:0> 0000 15:0 0000 32f0 dch3ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3300 dch3dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3310 dch3sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3320 dch3dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3330 dch3csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3340 dch3cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3350 dch3dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3360 dch4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3370 dch4econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3380 dch4int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3390 dch4ssa 31:16 chssa<31:0> 0000 15:0 0000 33a0 dch4dsa 31:16 chdsa<31:0> 0000 15:0 0000 table 4-19: dma channels 0-7 register map (1,2) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 91 pic32mx5xx/6xx/7xx 33b0 dch4ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz15:0> 0000 33c0 dch4dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 33d0 dch4sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 33e0 dch4dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 33f0 dch4csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3400 dch4cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3410 dch4dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3420 dch5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3430 dch5econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3440 dch5int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3450 dch5ssa 31:16 chssa<31:0> 0000 15:0 0000 3460 dch5dsa 31:16 chdsa<31:0> 0000 15:0 0000 3470 dch5ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3480 dch5dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3490 dch5sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 34a0 dch5dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 34b0 dch5csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 34c0 dch5cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 table 4-19: dma channels 0-7 register map (1,2) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 92 ? 2009-2011 microchip technology inc. 34d0 dch5dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 34e0 dch6con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 34f0 dch6econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 3500 dch6int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3510 dch6ssa 31:16 chssa<31:0> 0000 15:0 0000 3520 dch6dsa 31:16 chdsa<31:0> 0000 15:0 0000 3530 dch6ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3540 dch6dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3550 dch6sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3560 dch6dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3570 dch6csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3580 dch6cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3590 dch6dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 35a0 dch7con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 35b0 dch7econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? ff00 35c0 dch7int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 35d0 dch7ssa 31:16 chssa<31:0> 0000 15:0 0000 35e0 dch7dsa 31:16 chdsa<31:0> 0000 15:0 0000 table 4-19: dma channels 0-7 register map (1,2) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 93 pic32mx5xx/6xx/7xx 35f0 dch7ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3600 dch7dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3610 dch7sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3620 dch7dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3630 dch7csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3640 dch7cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3650 dch7dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 table 4-19: dma channels 0-7 register map (1,2) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: dma channels 4-7 are note available on pic32mx534/564/664/764 devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 94 ? 2009-2011 microchip technology inc. table 4-20: comparator register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a000 cm1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a010 cm2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ?coutevpol<1:0> ? cref ? ? cch<1:0> 00c3 a060 cmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? frz sidl ? ? ? ? ? ? ? ? ? ? ? c2out c1out 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-21: comparator voltage reference register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 cvrcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ?vrefsel (2) bgsel<1:0> (2) ? cvroe cvrr cvrss cvr<3:0> 0100 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: these bits are not available on pic32mx575/675/695/775 dev ices. on these devices, reset value for cvrcon is 0000 . free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 95 pic32mx5xx/6xx/7xx table 4-22: flash controller register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f400 nvmcon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 wr wren wrerr lvderr lvdstat ? ? ? ? ? ? ? nvmop<3:0> 0000 f410 nvmkey 31:16 nvmkey<31:0> 0000 15:0 0000 f420 nvmaddr (1) 31:16 nvmaddr<31:0> 0000 15:0 0000 f430 nvmdata 31:16 nvmdata<31:0> 0000 15:0 0000 f440 nvmsrc addr 31:16 nvmsrcaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respec tively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-23: system control register map (1,2) virtual address (bf80_#) register name bit range bits all resets (2) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f000 osccon 31:16 ? ? pllodiv<2:0> frcdiv<2:0> ? soscrdy ? pbdiv<1:0> pllmult<2:0> 0000 15:0 ?cosc<2:0> ? nosc<2:0> clklock ulock slock slpen cf ufrcen soscen oswen 0000 f010 osctun 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? tun<5:0> 0000 0000 wdtcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? swdtps<4:0> ? wdtclr 0000 f600 rcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cmr vregs extr swr ? wdto sleep idle bor por 0000 f610 rswrst 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?swrst 0000 f230 syskey 31:16 syskey<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 96 ? 2009-2011 microchip technology inc. table 4-24: porta register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 trisa 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisa15 trisa14 ? ? ? trisa10 trisa9 ? trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 c6ff 6010 porta 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ra15 ra14 ? ? ?ra10ra9 ? ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 6020 lata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lata15 lata14 ? ? ? lata10 lata9 ? lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx 6030 odca 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odca15 odca14 ? ? ? odca10 odca9 ? odca7 odca6 odca5 odca4 odca3 odca2 odca1 odca0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-25: portb register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6040 trisb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff 6050 portb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 6060 latb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx 6070 odcb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcb15 odcb14 odcb13 odcb12 odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 odcb3 odcb2 odcb1 odcb0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 97 pic32mx5xx/6xx/7xx table 4-26: portc register map for pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx764f128h, pic32mx775f256h, pic32m x775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? ? ? ? ? ? f000 6090 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 60a0 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 60b0 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcc15 odcc14 odcc13 odcc12 ? ? ? ? ? ? ? ? ? ? ? ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-27: portc register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? f00f 6090 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? xxxx 60a0 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? xxxx 60b0 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcc15 odcc14 odcc13 odcc12 ? ? ? ? ? ? ? odcc4 odcc3 odcc2 odcc1 ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. 2: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more infor- mation. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 98 ? 2009-2011 microchip technology inc. table 4-28: portd register map for pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60c0 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 0fff 60d0 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 60e0 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 60f0 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-29: portd register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60c0 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 ffff 60d0 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 60e0 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lat15 lat14 lat13 lat12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 60f0 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 odcd3 odcd2 odcd1 odcd0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 99 pic32mx5xx/6xx/7xx table 4-30: porte register map for pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 00ff 6110 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6120 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6130 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? odce7 0dce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-31: porte register map fo r pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 03ff 6110 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? re9 re8 re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6120 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ?late9late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6130 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odce9 odce8 odce7 0dce6 odce5 odce4 odce3 odce2 odce1 odce0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 100 ? 2009-2011 microchip technology inc. table 4-32: portf register map for pic32mx534f064h, pic32mx564f064 h, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? trisf5 trisf4 trisf3 ? trisf1 trisf0 003b 6150 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ?rf5rf4rf3 ?rf1rf0 xxxx 6160 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? latf5 latf4 latf3 ? latf1 latf0 xxxx 6170 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? odcf5 odcf4 odcf3 ? odcf1 odcf0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-33: portf register ma p pic32mx534f064l, pic32mx564f0 64l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx775f256l, pic32mx764f128l, pic32mx775f512 l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? trisf13 trisf12 ? ? ?trisf8 ? ? trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 313f 6150 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? rf13 rf12 ? ? ?rf8 ? ? rf5 rf4 rf3 rf2 rf1 rf0 xxxx 6160 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? latf13 latf12 ? ? ? latf8 ? ? latf5 latf4 latf3 latf2 latf1 latf0 xxxx 6170 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? odcf13 odcf12 ? ? ? odcf8 ? ? odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 101 pic32mx5xx/6xx/7xx table 4-34: portg register map fo r pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx664f064h, pic32mx664f128h, pi c32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx764f128h, pic32mx775f256h, pic32m x775f512h and pic32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 ? ? 03cc 6190 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 ? ? xxxx 61a0 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? latg9 latg8 latg7 latg6 ? ?latg3latg2 ? ? xxxx 61b0 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odcg9 odcg8 odcg7 odcg6 ? ? odcg3 odcg2 ? ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-35: portg register map for pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx764f128l, pic3 2mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisg15 trisg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 f3cf 6190 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rg15 rg14 rg13 rg12 ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 xxxx 61a0 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 xxxx 61b0 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcg15 odcg14 odcg13 odcg12 ? ? odcg9 odcg8 odcg7 odcg6 ? ? odcg3 odcg2 odcg1 odcg0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 102 ? 2009-2011 microchip technology inc. table 4-36: change notice and pull-up register map for pic32mx534f064l, pic32mx5 64f064l, pic32m x564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l, pic32mx695f512l, pic32mx 764f128l, pic32mx775f256l, pic32mx7 75f512 and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61c0 cncon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 61d0 cnen 31:16 ? ? ? ? ? ? ? ? ? ? cnen21 cnen20 cnen19 cnen18 cnen17 cnen16 0000 15:0 cnen15 cnen14 cnen13 cnen12 cnen11 cnen10 cnen9 cnen8 cnen7 cnen6 cnen5 cnen4 cnen3 cnen2 cnen1 cnen0 0000 61e0 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? cnpue21 cnpue20 cnpue19 cnpue18 cnpue17 cnpue16 0000 15:0 cnpue15 cnpue14 cnpue13 cnpue12 cnpue11 cnpue10 cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-37: change notice and pull-up register map for pic32mx575f256h, pic32mx5 75f512h, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h , pic32mx775f512h and pi c32mx795f512h devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61c0 cncon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 61d0 cnen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? cnen18 cnen17 cnen16 0000 15:0 cnen15 cnen14 cnen13 cnen12 cnen11 cnen10 cnen9 cnen8 cnen7 cnen6 cnen5 cnen4 cnen3 cnen2 cnen1 cnen0 0000 61e0 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? cnpue18 cnpue17 cnpue16 0000 15:0 cnpue15 cnpue14 cnpue13 cnpue12 cnpue11 cnpue10 cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpue3 cnpue2 cnpue1 cnpue0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 103 pic32mx5xx/6xx/7xx table 4-38: parallel mast er port register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 pmcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on frz sidl adrmux<1:0> pmpttl ptwren ptrden csf<1:0> alp cs2p cs1p ? wrsp rdsp 0000 7010 pmmode 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> waitb<1:0> waitm<3:0> waite<1:0> 0000 7020 pmaddr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cs2en/a15 cs1en/a14 addr<13:0> 0000 7030 pmdout 31:16 dataout<31:0> 0000 15:0 0000 7040 pmdin 31:16 datain<31:0> 0000 15:0 0000 7050 pmaen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pten<15:0> 0000 7060 pmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3e ob2e ob1e ob0e 008f legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. table 4-39: programming and diagnostics register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f200 ddpcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?jtagentroen ?tdoen 0008 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 104 ? 2009-2011 microchip technology inc. table 4-40: prefetch register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 checon (1,2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? checoh 0000 15:0 ? ? ? ? ? ? dcsz<1:0> ? ? prefen<1:0> ? pfmws<2:0> 0007 4010 cheacc (1) 31:16 chewen ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? cheidx<3:0> 0000 4020 chetag (1) 31:16 ltagboot ? ? ? ? ? ? ? ltag<23:16> 00xx 15:0 ltag<15:4> lvalid llock ltype ? xxx2 4030 chemsk (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lmask<15:5> ? ? ? ? ? 0000 4040 chew0 31:16 chew0<31:0> xxxx 15:0 xxxx 4050 chew1 31:16 chew1<31:0> xxxx 15:0 xxxx 4060 chew2 31:16 chew2<31:0> xxxx 15:0 xxxx 4070 chew3 31:16 chew3<31:0> xxxx 15:0 xxxx 4080 chelru 31:16 ? ? ? ? ? ? ? chelru<24:16> 0000 15:0 chelru<15:0> 0000 4090 chehit 31:16 chehit<31:0> xxxx 15:0 xxxx 40a0 chemis 31:16 chemis<31:0> xxxx 15:0 xxxx 40c0 chepfabt 31:16 chepfabt<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset value is dependent on devcfgx configuration. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 105 pic32mx5xx/6xx/7xx table 4-41: rtcc register map (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 rtccon 31:16 ? ? ? ? ? ? cal<9:0> 0000 15:0 on frz sidl ? ? ? ? ? rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe 0000 0210 rtcalrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 alrmen chime piv alrmsync amask<3:0> arpt<7:0> 0000 0220 rtctime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0230 rtcdate 31:16 year10<3:0> year01<3:0> month10<3:0> month01<3:0> xxxx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx00 0240 alrmtime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0250 alrmdate 31:16 ? ? ? ? ? ? ? ? month10<3:0> month01<3:0> 00xx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx0x legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 106 ? 2009-2011 microchip technology inc. table 4-42: devcfg: device configuration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2ff0 devcfg3 31:16 fvbusio fusbidio ? ? ? fcanio fethio fmiien ? ? ? ? ? fsrssel<2:0> xxxx 15:0 userid<15:0> xxxx 2ff4 devcfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? fpllodiv<2:0> xxxx 15:0 upllen ? ? ? ? upllidiv<2:0> ? fpllmul<2:0> ? fpllidiv<2:0> xxxx 2ff8 devcfg1 31:16 ? ? ? ? ? ? ? ?fwdten ? ? wdtps<4:0> xxxx 15:0 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> ieso ? fsoscen ? ? fnosc<2:0> xxxx 2ffc devcfg0 31:16 ? ? ?cp ? ? ?bwp ? ? ? ?pwp<7:4> xxxx 15:0 pwp<3:0> ? ? ? ? ? ? ? ? icesel ? debug<1:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-43: device and revision id summary (1) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f220 devid 31:16 ver<3:0> devid<27:16> xxxx 15:0 devid<15:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset values are dependent on the device variant. refer to ?pic32mx5xx/6xx/7xx family silicon errata and data sheet clarification? (ds80480) for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 107 pic32mx5xx/6xx/7xx table 4-44: usb register map (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 u1otgir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 5050 u1otgie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 5060 u1otgstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 5070 u1otgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 5080 u1pwrc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?uactpnd (4) ? ? uslpgrd usbbusy ? ususpend usbpwr 0000 5200 u1ir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallif attachif resumeif idleif trnif sofif uerrif urstif 0000 detachif 0000 5210 u1ie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallie attachie resumeie idleie trnie sofie uerrie urstie 0000 detachie 0000 5220 u1eir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 eofef 0000 5230 u1eie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 eofee 0000 5240 u1stat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? endpt<3:0> (4) dir ppbi ? ? 0000 5250 u1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?jstate (4) se0 (4) pktdis usbrst hosten resume ppbrst usben 0000 tokbusy sofen 0000 5260 u1addr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspden devaddr<6:0> 0000 5270 u1bdtp1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrl<7:1> ? 0000 5280 u1frml (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? frml<7:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 108 ? 2009-2011 microchip technology inc. 5290 u1frmh (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? frmh<2:0> 0000 52a0 u1tok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? pid<3:0> ep<3:0> 0000 52b0 u1sof 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cnt<7:0> 0000 52c0 u1bdtp2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrh<7:0> 0000 52d0 u1bdtp3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptru<7:0> 0000 52e0 u1cnfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? uteye uoemon usbfrz usbsidl ? ? ? uasuspnd 0001 5300 u1ep0 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspd retrydis ? epcondis eprxen eptxen epstall ephshk 0000 5310 u1ep1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5320 u1ep2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5330 u1ep3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5340 u1ep4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5350 u1ep5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5360 u1ep6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5370 u1ep7 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5380 u1ep8 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5390 u1ep9 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53a0 u1ep10 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-44: usb register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 109 pic32mx5xx/6xx/7xx 53b0 u1ep11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53c0 u1ep12 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53d0 u1ep13 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53e0 u1ep14 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53f0 u1ep15 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-44: usb register map (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an off set of 0x4, 0x8 and 0xc respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associated clr, set and inv registers. 4: reset value for this bit is undefined. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 110 ? 2009-2011 microchip technology inc. table 4-45: can1 register summary fo r pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx764f128h, pic32mx775f256h, pi c32mx775f512h, pic32mx795f512h, pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 b000 c1con 31:16 ? ? ? ? abat reqop<2:0> opmod<2:0> cancap ? ? ? ? 0480 15:0 on frz sidle ? canbusy ? ? ? ? ? ? dncnt<4:0> 0000 b010 c1cfg 31:16 ? ? ? ? ? ? ? ? ? wakfil ? ? ? seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 b020 c1int 31:16 ivrie wakie cerrie serrie rbovie ? ? ? ? ? ? ? modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif ? ? ? ? ? ? ? modif ctmrif rbif tbif 0000 b030 c1vec 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? filhit<4:0> ? icode<6:0> 0040 b040 c1trec 31:16 ? ? ? ? ? ? ? ? ? ? txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 b050 c1fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fi foip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 b060 c1rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 b070 c1tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 b080 c1rxm0 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b090 c1rxm1 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0a0 c1rxm2 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0b0 c1rxm3 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b0c0 c1fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 b0d0 c1fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 b0e0 c1fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 b0f0 c1fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 111 pic32mx5xx/6xx/7xx b100 c1fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0> 0000 b110 c1fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 b120 c1fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 b130 c1fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 b140 c1rxfn (n = 0-31) 31:16 sid<10:0> -? exid ? eid<17:16> xxxx 15:0 eid<15:0> xxxx b340 c1fifoba 31:16 c1fifoba<31:0> 0000 15:0 0000 b350 c1fifoconn (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ?fsize<4:0> 0000 15:0 ? freset uinc donly ? ? ? ? txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 b360 c1fifointn (n = 0-31) 31:16 ? ? ? ? ? txnfullie txhalfie txemptyie ? ? ? ? rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 ? ? ? ? ? txnfullif txhalfif txemptyif ? ? ? ? rxovflif rxfullif rxhalfif rxn emptyif 0000 b370 c1fifouan (n = 0-31) 31:16 c1fifoua<31:0> 0000 15:0 0000 b380 c1fifocin (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? c1fifoci<4:0> 0000 table 4-45: can1 register summary fo r pic32mx534f064h, PIC32MX564F064H, pic32mx564f128h, pic32mx575f256h, pic32mx575f512h, pic32mx764f128h, pic32mx775f256h, pi c32mx775f512h, pic32mx795f512h, pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l, pic32mx575f512l, pic32mx764f128l, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 112 ? 2009-2011 microchip technology inc. table 4-46: can2 register summary fo r pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 c000 c2con 31:16 ? ? ? ? abat reqop<2:0> opmod<2:0> cancap ? ? ? ? 0480 15:0 on frz sidle ? canbusy ? ? ? ? ? ? dncnt<4:0> 0000 c010 c2cfg 31:16 ? ? ? ? ? ? ? ? ? wakfil ? ? ? seg2ph<2:0> 0000 15:0 seg2phts sam seg1ph<2:0> prseg<2:0> sjw<1:0> brp<5:0> 0000 c020 c2int 31:16 ivrie wakie cerrie serrie rbovie ? ? ? ? ? ? ? modie ctmrie rbie tbie 0000 15:0 ivrif wakif cerrif serrif rbovif ? ? ? ? ? ? ? modif ctmrif rbif tbif 0000 c030 c2vec 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? filhit<4:0> ? icode<6:0> 0040 c040 c2trec 31:16 ? ? ? ? ? ? ? ? ? ? txbo txbp rxbp txwarn rxwarn ewarn 0000 15:0 terrcnt<7:0> rerrcnt<7:0> 0000 c050 c2fstat 31:16 fifoip31 fifoip30 fifoip29 fifoip28 fifoip27 fifoip26 fifoip25 fifoip24 fifoip23 fifoip22 fifoip21 fifoip20 fifoip19 fifoip18 fifoip17 fi foip16 0000 15:0 fifoip15 fifoip14 fifoip13 fifoip12 fifoip11 fifoip10 fifoip9 fifoip8 fifoip7 fifoip6 fifoip5 fifoip4 fifoip3 fifoip2 fifoip1 fifoip0 0000 c060 c2rxovf 31:16 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 15:0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 c070 c2tmr 31:16 cants<15:0> 0000 15:0 cantspre<15:0> 0000 c080 c2rxm0 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0a0 c2rxm1 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0b0 c2rxm2 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0b0 c2rxm3 31:16 sid<10:0> -? mide ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c0c0 c2fltcon0 31:16 flten3 msel3<1:0> fsel3<4:0> flten2 msel2<1:0> fsel2<4:0> 0000 15:0 flten1 msel1<1:0> fsel1<4:0> flten0 msel0<1:0> fsel0<4:0> 0000 c0d0 c2fltcon1 31:16 flten7 msel7<1:0> fsel7<4:0> flten6 msel6<1:0> fsel6<4:0> 0000 15:0 flten5 msel5<1:0> fsel5<4:0> flten4 msel4<1:0> fsel4<4:0> 0000 c0e0 c2fltcon2 31:16 flten11 msel11<1:0> fsel11<4:0> flten10 msel10<1:0> fsel10<4:0> 0000 15:0 flten9 msel9<1:0> fsel9<4:0> flten8 msel8<1:0> fsel8<4:0> 0000 c0f0 c2fltcon3 31:16 flten15 msel15<1:0> fsel15<4:0> flten14 msel14<1:0> fsel14<4:0> 0000 15:0 flten13 msel13<1:0> fsel13<4:0> flten12 msel12<1:0> fsel12<4:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 113 pic32mx5xx/6xx/7xx c100 c2fltcon4 31:16 flten19 msel19<1:0> fsel19<4:0> flten18 msel18<1:0> fsel18<4:0> 0000 15:0 flten17 msel17<1:0> fsel17<4:0> flten16 msel16<1:0> fsel16<4:0: 0000 c110 c2fltcon5 31:16 flten23 msel23<1:0> fsel23<4:0> flten22 msel22<1:0> fsel22<4:0> 0000 15:0 flten21 msel21<1:0> fsel21<4:0> flten20 msel20<1:0> fsel20<4:0> 0000 c120 c2fltcon6 31:16 flten27 msel27<1:0> fsel27<4:0> flten26 msel26<1:0> fsel26<4:0> 0000 15:0 flten25 msel25<1:0> fsel25<4:0> flten24 msel24<1:0> fsel24<4:0> 0000 c130 c2fltcon7 31:16 flten31 msel31<1:0> fsel31<4:0> flten30 msel30<1:0> fsel30<4:0> 0000 15:0 flten29 msel29<1:0> fsel29<4:0> flten28 msel28<1:0> fsel28<4:0> 0000 c140 c2rxfn (n = 0-31) 31:16 sid<10:0> -? exid ? eid<17:16> xxxx 15:0 eid<15:0> xxxx c340 c2fifoba 31:16 c2fifoba<31:0> 0000 15:0 0000 c350 c2fifoconn (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? fsize<4:0> 0000 15:0 ? freset uinc donly ? ? ? ? txen txabat txlarb txerr txreq rtren txpri<1:0> 0000 c360 c2fifointn (n = 0-31) 31:16 ? ? ? ? ? txnfullie txhalfie txemptyie ? ? ? ? rxovflie rxfullie rxhalfie rxn emptyie 0000 15:0 ? ? ? ? ? txnfullif txhalfif txemptyif ? ? ? ? rxovflif rxfullif rxhalfif rxn emptyif 0000 c370 c2fifouan (n = 0-31) 31:16 c2fifoua<31:0> 0000 15:0 0000 c380 c2fifocin (n = 0-31) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? c2fifoci<4:0> 0000 table 4-46: can2 register summary fo r pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 114 ? 2009-2011 microchip technology inc. table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, pic32mx764f128l, pic32mx775f256l, pic32mx775f512 l and pic32mx795f512l devices (1) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ethcon1 31:16 ptv<15:0> 0000 15:0 on frz sidl ? ? ? txrts rxen autofc ? ?manfc ? ? ? bufcdec 0000 9010 ethcon2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? rxbufsz<6:0> ? ? ? ? 0000 9020 ethtxst 31:16 txstaddr<31:16> 0000 15:0 txstaddr<15:2> ? ? 0000 9030 ethrxst 31:16 rxstaddr<31:16> 0000 15:0 rxstaddr<15:2> ? ? 0000 9040 ethht0 31:16 ht<31:0> 0000 15:0 0000 9050 ethht1 31:16 ht<63:32> 0000 15:0 0000 9060 ethpmm0 31:16 pmm<31:0> 0000 15:0 0000 9070 ethpmm1 31:16 pmm<63:32> 0000 15:0 0000 9080 ethpmcs 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pmcs<15:0> 0000 9090 ethpmo 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pmo<15:0> 0000 90a0 ethrxfc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 hten mpen ? notpm pmmode<3:0> crc erren crc oken runt erren runten ucen not meen mcen bcen 0000 90b0 ethrxwm 31:16 ? ? ? ? ? ? ? ?rxfwm<7:0> 0000 15:0 ? ? ? ? ? ? ? ? rxewm<7:0> 0000 90c0 ethien 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? tx buseie rx buseie ? ? ? ew markie fw markie rx doneie pk tpendie rx actie ? tx doneie tx abortie rx bufnaie rx ovflwie 0000 90d0 ethirq 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? txbuse rxbuse ? ? ? ewmark fwmark rxdone pktpend rxact ? txdone txabort rxbufna rxovflw 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip technology inc. ds61156g-page 115 pic32mx5xx/6xx/7xx 90e0 ethstat 31:16 ? ? ? ? ? ? ? ? bufcnt<7:0> 0000 15:0 ? ? ? ? ? ? ? ? busy txbusy rxbusy ? ? ? ? ? 0000 9100 eth rxovflow 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rxovflwcnt<15:0> 0000 9110 eth frmtxok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 frmtxokcnt<15:0> 0000 9120 eth scolfrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 scolfrmcnt<15:0> 0000 9130 eth mcolfrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mcolfrmcnt<15:0> 0000 9140 eth frmrxok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 frmrxokcnt<15:0> 0000 9150 eth fcserr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 fcserrcnt<15:0> 0000 9160 eth algnerr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 algnerrcnt<15:0> 0000 9200 emac1 cfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 soft reset sim reset ? ? reset rmcs reset rfun reset tmcs reset tfun ? ? ? loopback txpause rxpause passall rxenable 800d 9210 emac1 cfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? excess dfr bp nobkoff nobkoff ? ? longpre purepre autopad vlanpad pad enable crc enable delaycrc hugefrm lengthck fulldplx 4082 9220 emac1 ipgt 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? b2bipktgp<6:0> 0012 9230 emac1 ipgr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? nb2bipktgp1<6:0> ? nb2bipktgp2<6:0> 0c12 9240 emac1 clrt 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cwindow<5:0> ? ? ? ?retx<3:0> 370f 9250 emac1 maxf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 macmaxf<15:0> 05ee table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, pic32mx764f128l, pic32mx775f256l, pic32mx775f512 l and pic32mx795f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 116 ? 2009-2011 microchip technology inc. 9260 emac1 supp 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? reset rmii ? ? speed rmii ? ? ? ? ? ? ? ? 1000 9270 emac1 test 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? testbp testpause shrtqnta 0000 9280 emac1 mcfg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 reset mgmt ? ? ? ? ? ? ? ? ? clksel<3:0> nopre scaninc 0020 9290 emac1 mcmd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ?scanread 0000 92a0 emac1 madr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? phyaddr<4:0> ? ? ? regaddr<4:0> 0100 92b0 emac1 mwtd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mwtd<15:0> 0000 92c0 emac1 mrdd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 mrdd<15:0> 0000 92d0 emac1 mind 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? linkfail notvalid scan miimbusy 0000 9300 emac1 sa0 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr6<7:0> stnaddr5<7:0> xxxx 9310 emac1 sa1 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr4<7:0> stnaddr3<7:0> xxxx 9320 emac1 sa2 (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? xxxx 15:0 stnaddr2<7:0> stnaddr1<7:0> xxxx table 4-47: ethernet controller register summary for pic32mx664f064h, pic32mx664f128h, pic32mx664f064l, pic32mx664f128l, pic32mx675f256h, pic32mx675f512h, pic32mx695f512h, pic32mx775f256h, pic32mx775f512h, pic32mx795f512h, pic32mx695f512l, pi c32mx675f256l, pic32mx675f512l, pic32mx764f128h, pic32mx764f128l, pic32mx775f256l, pic32mx775f512 l and pic32mx795f512l devices (1) (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table (with the exception of ethstat) have corresponding clr, set and inv registers at their virtual addr esses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.1.1 ?clr, set and inv registers? for more information. 2: reset values default to the factory programmed value. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 117 pic32mx5xx/6xx/7xx 5.0 flash program memory pic32mx5xx/6xx/7xx devices contain an internal flash program memory for ex ecuting user code. there are three methods by which the user can program this memory: 1. run-time self-programming (rtsp) 2. ejtag programming 3. in-circuit serial programming? (icsp?) rtsp is performed by software executing from either flash or ram memory. information about rtsp techniques is available in section 5. ?flash program memory? (ds61121) in the ?pic32 family reference manual?. ejtag is performed using the ejtag port of the device and an ejtag capable programmer. icsp is performed using a serial data connection to the device and allows much faster programming times than rtsp. the ejtag and icsp methods are described in the ? pic32 flash programming specification ? (ds61145), which can be downloaded from the microchip web site. note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. ?flash program memory? (ds61121) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 118 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 119 pic32mx5xx/6xx/7xx 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the following is a list of device reset sources: ? por: power-on reset ?mclr : master clear reset pin ? swr: software reset ? wdtr: watchdog timer reset ? bor: brown-out reset ? cmr: configuration mismatch reset a simplified block diagram of the reset module is illustrated in figure 6-1 . figure 6-1: system reset block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 7. ?resets? (ds61118) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. mclr v dd v dd rise detect por sleep or idle brown-out reset wdt time-out glitch filter bor configuration sysrst software reset power-up timer voltage enabled reset wdtr swr cmr mclr mismatch regulator free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 120 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 121 pic32mx5xx/6xx/7xx 7.0 interrupt controller pic32mx5xx/6xx/7xx devices generate interrupt requests in response to inte rrupt events from peripheral modules. the interrupt cont rol module exists externally to the cpu logic and prioritizes the interrupt events before presenting them to the cpu. the pic32mx5xx/6xx/7xx in terrupt module includes the following features: ? up to 96 interrupt sources ? up to 64 interrupt vectors ? single and multi-vector mode operations ? five external interrupts with edge polarity control ? interrupt proximity timer ? module freeze in debug mode ? seven user-selectable priority levels for each vector ? four user-selectable subpriority levels within each priority ? dedicated shadow set for user-selectable priority level ? software can generate any interrupt ? user-configurable interrupt vector table location ? user-configurable interrupt vector spacing a simplified block diagram of the interrupt controller module is illustrated in figure 7-1 . figure 7-1: interrupt controller module note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?interrupts? (ds61108) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. interrupt controller interrupt requests vector number cpu core priority level shadow set number free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 122 ? 2009-2011 microchip technology inc. table 7-1: interrupt irq, vector and bit location interrupt source (1) irq vector number interrupt bit location flag enable priority sub-priority highest natural order priority ct ? core timer interrupt 0 0 ifs0<0> iec0<0> ipc0<4:2> ipc0<1:0> cs0 ? core software interrupt 0 1 1 ifs0<1> iec0<1> ipc0<12:10> ipc0<9:8> cs1 ? core software interrupt 1 2 2 ifs0<2> iec0<2> ipc0<20:18> ipc0<17:16> int0 ? external interrupt 0 3 3 ifs0<3> iec0<3> ipc0<28:26> ipc0<25:24> t1 ? timer1 4 4 ifs0<4> iec0<4> ipc1<4:2> ipc1<1:0> ic1 ? input capture 1 5 5 ifs0<5> iec0<5> ipc1<12:10> ipc1<9:8> oc1 ? output compare 1 6 6 ifs0<6> iec0<6> ipc1<20:18> ipc1<17:16> int1 ? external interrupt 1 7 7 ifs0<7> iec0<7> ipc1<28:26> ipc1<25:24> t2 ? timer2 8 8 ifs0<8> iec0<8> ipc2<4:2> ipc2<1:0> ic2 ? input capture 2 9 9 ifs0<9> iec0<9> ipc2<12:10> ipc2<9:8> oc2 ? output compare 2 10 10 ifs0<10> iec0<10> ipc2<20:18> ipc2<17:16> int2 ? external interrupt 2 11 11 ifs0<11> iec0<11> ipc2<28:26> ipc2<25:24> t3 ? timer3 12 12 ifs0<12> iec0<12> ipc3<4:2> ipc3<1:0> ic3 ? input capture 3 13 13 ifs0<13> iec0<13> ipc3<12:10> ipc3<9:8> oc3 ? output compare 3 14 14 ifs0<14> iec0<14> ipc3<20:18> ipc3<17:16> int3 ? external interrupt 3 15 15 ifs 0<15> iec0<15> ipc3<28:26> ipc3<25:24> t4 ? timer4 16 16 ifs0<16> iec0<16> ipc4<4:2> ipc4<1:0> ic4 ? input capture 4 17 17 ifs0<17> iec0<17> ipc4<12:10> ipc4<9:8> oc4 ? output compare 4 18 18 ifs0<18> iec0<18> ipc4<20:18> ipc4<17:16> int4 ? external interrupt 4 19 19 ifs 0<19> iec0<19> ipc4<28:26> ipc4<25:24> t5 ? timer5 20 20 ifs0<20> iec0<20> ipc5<4:2> ipc5<1:0> ic5 ? input capture 5 21 21 ifs0<21> iec0<21> ipc5<12:10> ipc5<9:8> oc5 ? output compare 5 22 22 ifs0<22> iec0<22> ipc5<20:18> ipc5<17:16> spi1e ? spi1 fault 23 23 ifs0<23> iec0<23> ipc5<28:26> ipc5<25:24> spi1rx ? spi1 receive done 24 23 ifs0<24> iec0<24> ipc5<28:26> ipc5<25:24> spi1tx ? spi1 transfer done 25 23 ifs0<25> iec0<25> ipc5<28:26> ipc5<25:24> u1e ? uart1 error 26 24 ifs0<26> iec0<26> ipc6<4:2> ipc6<1:0> spi3e ? spi3 fault i2c3b ? i2c3 bus collision event u1rx ? uart1 receiver 27 24 ifs0<27> iec0<27> ipc6<4:2> ipc6<1:0> spi3rx ? spi3 receive done i2c3s ? i2c3 slave event u1tx ? uart1 transmitter 28 24 ifs0<28> iec0<28> ipc6<4:2> ipc6<1:0> spi3tx ? spi3 transfer done i2c3m ? i2c3 master event i2c1b ? i2c1 bus collision event 29 25 ifs0<29> iec0<29> ipc6<12:10> ipc6<9:8> i2c1s ? i2c1 slave event 30 25 ifs0<30> iec0<30> ipc6<12:10> ipc6<9:8> i2c1m ? i2c1 master event 31 25 ifs0<31> iec0<31> ipc6<12:10> ipc6<9:8> cn ? input change interrupt 32 26 ifs1<0> iec1<0> ipc6<20:18> ipc6<17:16> ad1 ? adc1 convert done 33 27 ifs1<1> iec1<1> ipc6<28:26> ipc6<25:24> note 1: not all interrupt sources are available on all devices. see table 1 , ta b l e 2 and ta b l e 3 for the list of available peripherals. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 123 pic32mx5xx/6xx/7xx pmp ? parallel master port 34 28 ifs1<2> iec1<2> ipc7<4:2> ipc7<1:0> cmp1 ? comparator interrupt 35 29 ifs1<3> iec1<3> ipc7<12:10> ipc7<9:8> cmp2 ? comparator interrupt 36 30 ifs1<4> iec1<4> ipc7<20:18> ipc7<17:16> u3e ? uart2a error spi2e ? spi2 fault i2c4b ? i2c4 bus collision event 37 31 ifs1<5> iec1<5> ipc7<28:26> ipc7<25:24> u3rx ? uart2a receiver spi2rx ? spi2 receive done i2c4s ? i2c4 slave event 38 31 ifs1<6> iec1<6> ipc7<28:26> ipc7<25:24> u3tx ? uart2a transmitter spi2tx ? spi2 transfer done ic4m ? i2c4 master event 39 31 ifs1<7> iec1<7> ipc7<28:26> ipc7<25:24> u2e ? uart3a error spi4e ? spi4 fault i2c5b ? i2c5 bus collision event 40 32 ifs1<8> iec1<8> ipc8<4:2> ipc8<1:0> u2rx ? uart3a receiver spi4rx ? spi4 receive done i2c5s ? i2c5 slave event 41 32 ifs1<9> iec1<9> ipc8<4:2> ipc8<1:0> u2tx ? uart3a transmitter spi4tx ? spi4 transfer done ic5m ? i2c5 master event 42 32 ifs1<10> iec1<10> ipc8<4:2> ipc8<1:0> i2c2b ? i2c2 bus collision event 43 33 ifs1<11> iec1<11> ipc8<12:10> ipc8<9:8> i2c2s ? i2c2 slave event 44 33 ifs1<12> iec1<12> ipc8<12:10> ipc8<9:8> i2c2m ? i2c2 master event 45 33 ifs1<13> iec1<13> ipc8<12:10> ipc8<9:8> fscm ? fail-safe clock monitor 46 34 ifs1<14> iec1<14> ipc8<20:18> ipc8<17:16> rtcc ? real-time clock and calendar 47 35 ifs1<15> iec1<15> ipc8<28:26> ipc8<25:24> dma0 ? dma channel 0 48 36 ifs1<16> iec1<16> ipc9<4:2> ipc9<1:0> dma1 ? dma channel 1 49 37 ifs1<17> iec1<17> ipc9<12:10> ipc9<9:8> dma2 ? dma channel 2 50 38 ifs1<18> iec1<18> ipc9<20:18> ipc9<17:16> dma3 ? dma channel 3 51 39 ifs1<19> iec1<19> ipc9<28:26> ipc9<25:24> dma4 ? dma channel 4 52 40 ifs1<20> iec1<20> ipc10<4:2> ipc10<1:0> dma5 ? dma channel 5 53 41 ifs1<21> iec1<21> ipc10<12:10> ipc10<9:8> dma6 ? dma channel 6 54 42 ifs1<22> iec1<22> ipc10<20:18> ipc10<17:16> dma7 ? dma channel 7 55 43 ifs1<23> iec1<23> ipc10<28:26> ipc10<25:24> fce ? flash control event 56 44 ifs1<24> iec1<24> ipc11<4:2> ipc11<1:0> usb ? usb interrupt 57 45 ifs1<25> iec1<25> ipc11<12:10> ipc11<9:8> can1 ? control area network 1 58 46 ifs1<26> iec1<26> ipc11<20:18> ipc11<17:16> can2 ? control area network 2 59 47 ifs1<27> iec1<27> ipc11<28:26> ipc11<25:24> eth ? ethernet interrupt 60 48 ifs1< 28> iec1<28> ipc12<4:2> ipc12<1:0> ic1e ? input capture 1 error 61 5 ifs1<29> iec1<29> ipc1<12:10> ipc1<9:8> ic2e ? input capture 2 error 62 9 ifs1<30> iec1<30> ipc2<12:10> ipc2<9:8> ic3e ? input capture 3 error 63 13 ifs1<31> iec1<31> ipc3<12:10> ipc3<9:8> ic4e ? input capture 4 error 64 17 ifs2<0> iec2<0> ipc4<12:10> ipc4<9:8> table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq vector number interrupt bit location flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1 , ta b l e 2 and ta b l e 3 for the list of available peripherals. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 124 ? 2009-2011 microchip technology inc. ic4e ? input capture 5 error 65 21 ifs2<1> iec2<1> ipc5<12:10> ipc5<9:8> pmpe ? parallel master port error 66 28 ifs2<2> iec2<2> ipc7<4:2> ipc7<1:0> u4e ? uart4 error 67 49 ifs2<3> iec2<3> ipc12<12:10> ipc12<9:8> u4rx ? uart4 receiver 68 49 ifs2<4> iec2<4> ipc12<12:10> ipc12<9:8> u4tx ? uart4 transmitter 69 49 ifs2<5> iec2<5> ipc12<12:10> ipc12<9:8> u6e ? uart6 error 70 50 ifs2<6> iec2<6> ipc12<20:18> ipc12<17:16> u6rx ? uart6 receiver 71 50 ifs2<7> iec2<7> ipc12<20:18> ipc12<17:16> u6tx ? uart6 transmitter 72 50 ifs2<8> iec2<8> ipc12<20:18> ipc12<17:16> u5e ? uart5 error 73 51 ifs2<9> iec2<9> ipc12<28:26> ipc12<25:24> u5rx ? uart5 receiver 74 51 ifs2<10> iec2<10> ipc12<28:26> ipc12<25:24> u5tx ? uart5 transmitter 75 51 ifs2<11> iec2<11> ipc12<28:26> ipc12<25:24> (reserved) ? ? ? ? ? ? lowest natural order priority table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq vector number interrupt bit location flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1 , ta b l e 2 and ta b l e 3 for the list of available peripherals. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 125 pic32mx5xx/6xx/7xx 8.0 oscillator configuration the pic32mx5xx/6xx/7xx oscillator system has the following modules and features: ? a total of four external and internal oscillator options as clock sources ? on-chip pll with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources ? on-chip user-selectable divisor postscaler on select oscillator sources ? software-controllable switching between various clock sources ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown ? dedicated on-chip pll for usb peripheral figure 8-1 shows the oscillator module block diagram. figure 8-1: pic32mx5xx/6xx/7xx fa mily oscillator block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 6. ?oscillator? (ds61112) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. timer1, rtcc clock control logic fail-safe clock monitor fscm int fscm event cosc<2:0> nosc<2:0> oswen fscmen<1:0> pll secondary oscillator (s osc ) soscen and fsoscen sosco sosci primary oscillator xtpll, hspll, xt, hs, ec cpu and select peripherals peripherals frcdiv<2:0> wdt, pwrt 8 mhz typical frc 31.25 khz typical frc oscillator lprc oscillator s osc lprc frcdiv ecpll, frcpll tun<5:0> div 16 postscaler fpllidiv<2:0> pbdiv<1:0> frc/16 postscaler pll multiplier cosc<2:0> f in div x div y pll output divider pllodiv<2:0> pll input divider div x 32.768 khz pllmult<2:0> pbclk uf in = 4 mhz pll x24 usb clock (48 mhz) div 2 upllen ufrcen div x upllidiv<2:0> uf in 4 mhz f in 5 mhz c1 (3) c2 (3) xtal r s (1) enable notes: 1. a series resistor, r s , may be required for at strip cut crystals. 2. the internal feedback resistor, r f , is typically in the range of 2 to 10 m . 3. refer to section 6. ?oscillator ? (ds61112) in the ? pic32 family reference manual ? for help in determining the best oscillator components. 4. the pbclk out is available on the osc2 pin in certain clock modes. osc2 (4) osc1 r f (2) to internal logic usb pll (p osc ) div 2 adc sysclk free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 126 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 127 pic32mx5xx/6xx/7xx 9.0 prefetch cache prefetch cache increases performance for applications executing out of the cacheable program flash memory regions by implementing inst ruction caching, constant data caching and instruction prefetching. 9.1 features ? 16 fully associative lockable cache lines ? 16-byte cache lines ? up to four cache lines allocated to data ? two cache lines with address mask to hold repeated instructions ? pseudo lru replacement policy ? all cache lines are software writable ? 16-byte parallel memory fetch ? predictive instruction prefetch a simplified block diagram of the prefetch cache module is illustrated in figure 9-1 . figure 9-1: prefetch cache module block diagram note 1: this data sheet summ arizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. ?prefetch cache? (ds61119) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. hit logic tag logic cache line cache line address encode fsm bus ctrl cache ctrl prefetch ctrl hit lru miss lru rdata rdata ctrl ctrl ctrl pfm bmx/cpu bmx/cpu prefetch prefetch tag pre-fetch pre-fetch prefetch prefetch free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 128 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 129 pic32mx5xx/6xx/7xx 10.0 direct memory access (dma) controller the pic32 direct memory acce ss (dma) controller is a bus master module useful for data transfers between different devices without cpu intervention. the source and destination of a dma transfer can be any of the memory mapped modules existent in the pic32 (such as peripheral bus (pbus) devices: spi, uart, pmp, etc.) or memory itself. following are some of the key features of the dma controller module: ? four identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers - memory to memory and memory to peripheral transfers ? automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination ? fixed priority channel arbitration ? flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repeat block transfer modes - channel-to-channel chaining ? flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - pattern (data) match transfer termination ? multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half full - dma transfer aborted due to an external event - invalid dma address generated ? dma debug support features: - most recent address accessed by a dma channel - most recent dma channel to transfer data ? crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable figure 10-1: dma block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 31. ?direct memory access (dma) controller? (ds61117) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. address decoder channel 0 control channel 1 control channel n control global control (dmacon) bus interface channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq int controller device bus + bus arbitration peripheral bus free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 130 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 131 pic32mx5xx/6xx/7xx 11.0 usb on-the-go (otg) the universal serial bus (usb) module contains analog and digital components to provide a usb 2.0 full-speed and low-speed embedded host, full-speed device or otg implementation with a minimum of external components. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), a dedicated usb dma control- ler, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32 usb otg module is presented in figure 11-1 . the clock generator provides the 48 mhz clock required for usb full-speed and low-speed communi- cation. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides the analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. the usb dma controller transfers data between the data buffers in ram and the sie. the inte- grated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. the pic32 usb module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb otg support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? transaction handshaking performed by hardware ? endpoint buffering anywhere in system ram ? integrated dma to acce ss system ram and flash note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 27. ?usb on- the-go (otg)? (ds61126) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: the implementation and use of the usb specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigating and satisfying any applicable licensing obligations. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 132 ? 2009-2011 microchip technology inc. figure 11-1: pic32mx5xx/6xx/7xx family usb interface diagram osc1 osc2 primary oscillator 8mhztypical frc oscillator tun<5:0> (4) pll 48 mhz usb clock (7) div x upllen (6) (pb out) (1) ufrcen (3) (p osc ) upllidiv (6) uf in (5) div 2 v usb d+ (2) d- (2) id (8) bus transceiver sie v buson (8) comparators usb srp charge srp discharge registers and control interface transceiver power 3.3v to clock generator for core and peripherals sleep or idle sleep usben usb suspend cpu clock not p osc usb module voltage system ram usb suspend full speed pull-up host pull-down low speed pull-up host pull-down id pull-up dma note 1: pb clock is only available on th is pin for select ec modes. 2: pins can be used as digital inputs when usb is not enabled. 3: this bit field is contai ned in the osccon register. 4: this bit field is contained in the osctrm register. 5: usb pll u f in requirements: 4 mhz. 6: this bit field is contained in the devcfg2 register. 7: a 48 mhz clock is required for proper usb operation. 8: pins can be used as gpio wh en the usb module is disabled. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 133 pic32mx5xx/6xx/7xx 12.0 i/o ports general purpose i/o pins are the simplest of peripher- als. they allow the pic ? mcu to monitor and control other devices. to add flexib ility and functionality, some pins are multiplexed with alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. following are some of the key features of this module: ? individual output pin open-drain enable/disable ? individual input pin weak pull-up enable/disable ? monitor selective inputs and generate interrupt when change in pin state is detected ? operation during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 12-1 illustrates a block diagram of a typical multiplexed i/o port. figure 12-1: block diagram of a ty pical multiplexed port structure note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?i/o ports? (ds61120) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris 0 1 rd odc sysclk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 sysclk wr odc odc tris lat sleep 1 0 1 0 output multiplexers i/o cell synchronization r peripheral input legend: r = peripheral input buffer types may vary. refer to ta b l e 1 - 1 for peripheral details. note: this block diagram is a general representation of a shared port/ peripheral structure for illustration purposes only. the actual structure for any specific port/peripheral combination may be different than it is shown here. peripheral input buffer free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 134 ? 2009-2011 microchip technology inc. 12.1 parallel i/o (pio) ports all port pins have three registers (tris, lat and port) that are directly associated with their operation. tris is a data direction or tri-state control register that determines whether a digital pin is an input or an output. setting a trisx register bit = 1 , configures the corresponding i/o pin as an input; setting a trisx register bit = 0 , configures the corresponding i/o pin as an output. all port i/o pins are defined as inputs after a device reset. certain i/o pins are shared with analog peripherals and default to analog inputs after a device reset. port is a register used to read the current state of the signal applied to the port i/o pins. writing to a portx register performs a write to the port?s latch, latx register, latching the data to the port?s i/o pins. lat is a register used to write data to the port i/o pins. the latx latch register holds the data written to either the latx or portx registers. reading the latx latch register reads the last value written to the corresponding port or latch register. not all port i/o pins are implemented on some devices, therefore, the corresponding portx, latx and trisx register bits will read as zeros. 12.1.1 clr, set and inv registers every i/o module register has a corresponding clr (clear), set (set) and inv (invert) register designed to provide fast atomic bit manipulations. as the name of the register implies, a value written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ? 1 ? are modified. bits specified as ? 0 ? are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. 12.1.2 digital inputs pins are configured as digital inputs by setting the corresponding tris register bits = 1 . when configured as inputs, they are either ttl buffers or schmitt triggers. several digital pins share functionality with analog inputs and default to the analog inputs at por. setting the corresponding bit in the ad1pcfg register = 1 enables the pin as a digital pin. the maximum input voltage allowed on the input pins is the same as the maximum v ih specification. refer to section 31.0 ?electri cal characteristics? for v ih specification details. 12.1.3 analog inputs certain pins can be configured as analog inputs used by the adc and comparator modules. setting the corresponding bits in the ad1pcfg register = 0 enables the pin as an analog input pin and must have the corresponding tris bit set = 1 (input). if the tris bit is cleared = 0 (output), the digital output level (v oh or v ol ) will be converted. any time a port i/o pin is configured as analog, its digital input is disabled and the corresponding portx register bit will read ? 0 ?. the ad1pcfg register has a default value of 0x0000; therefore, all pins that share anx functions are analog (not digital) by default. 12.1.4 digital outputs pins are configured as digital outputs by setting the corresponding tris register bits = 0 . when configured as digital outputs, these pins are cmos drivers or can be configured as open-drain outputs by setting the corresponding bits in the open-drain configuration (odcx) register. the open-drain feature allows generation of outputs higher than v dd (e.g., 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see the ? pin diagrams ? section for the available pins and their functionality. 12.1.5 analog outputs certain pins can be configured as analog outputs, such as the cv ref output voltage used by the comparator module. configuring the comparator reference module to provide this output will present the analog output voltage on the pin, independent of the tris register setting for the corresponding pin. 12.1.6 input change notification the input change notification function of the i/o ports (cnx) allows devices to gen erate interrupt requests in response to change-of-state on selected pin. each cnx pin also has a weak pull-up, which acts as a current source connected to the pin. the pull-ups are enabled by setting the corresponding bit in the cnpue register. note: using a portxinv register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions, as compared to the traditional read-m odify-write method shown below: portc ^ = 0x0001 ; note: analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 135 pic32mx5xx/6xx/7xx 13.0 timer1 this family of pic32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applica- tions and counting external events. this timer can also be used with the low-power secondary oscillator (s osc ) for real-time clock (rtc) applications. the following modes are supported: ? synchronous internal timer ? synchronous internal gated timer ? synchronous external timer ? asynchronous external timer 13.1 additional supported features ? selectable clock prescaler ? timer operation during cpu idle and sleep mode ? fast bit manipulation using clr, set and inv registers ? asynchronous mode can be used with the s osc to function as a real-time clock (rtc) a simplified block diagram of the timer1 module is illustrated in figure 13-1 . figure 13-1: timer1 block diagram (1) note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds61105) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. on (t1con<15>) sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen event flag 1 0 tsync (t1con<2>) tgate (t1con<7>) tgate (t1con<7>) pbclk 1 0 tcs (t1con<1>) gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q qd (t1con<5:4>) note 1: the default state of the soscen (osccon<1>) during a device reset is controlled by the fsoscen bit in configuration word, devcfg1. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 136 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 137 pic32mx5xx/6xx/7xx 14.0 timer2/3, timer4/5 this family of pic32 devices features four synchronous 16-bit timers (default) that can operate as a free- running interval timer for various timing applications and counting external events. the following modes are supported: ? synchronous internal 16-bit timer ? synchronous internal 16-bit gated timer ? synchronous external 16-bit timer two 32-bit synchronous timers are available by combining timer2 with timer3 and timer4 with timer5. the 32-bit timers can operate in three modes: ? synchronous internal 32-bit timer ? synchronous internal 32-bit gated timer ? synchronous external 32-bit timer 14.1 additional supported features ? selectable clock prescaler ? timers operational during cpu idle ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc event trigger (timer3 only) ? fast bit manipulation using clr, set and inv registers figure 14-1: timer2/3, 4/5 block diagram (16-bit) note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds61105) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: in this chapter, references to registers, txcon, tmrx and prx, use ?x? to repre- sent timer2 through 5 in 16-bit modes. in 32-bit modes, ?x? represents timer2 or 4; ?y? represents timer3 or 5. sync prx txif equal comparator x 16 tmrx reset event flag q q d tgate (txcon<7>) 1 0 gate txck (2) sync on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk trigger (1) adc event note 1: adc event trigger is av ailable on timer3 only. 2: txck pins are not avai lable on 64-pin devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 138 ? 2009-2011 microchip technology inc. figure 14-2: timer2/3, 4/5 block diagram (32-bit) (1) tmry tmrx tyif event equal 32-bit comparator pry prx reset ls half word ms half word flag note 1: in this diagram, the use of ?x? in regi sters, txcon, tmrx, prx and txck, refers to either timer2 or timer4; the use of ?y? in registers, tycon, tmry, pry, ty if, refers to either timer3 or timer5. 2: txck pins are not avai lable on 64-pin devices. 3: adc event trigger is available only on the timer2/3 pair. tgate (txcon<7>) 0 1 pbclk gate txck (2) sync sync adc event trigger (3) on (txcon<15>) tgate (txcon<7>) tcs (txcon<1>) tckps (txcon<6:4>) prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q q d x 1 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 139 pic32mx5xx/6xx/7xx 15.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the input capture module captures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. the following events cause capture events: 1. simple capture event modes - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling) 3. capture timer value on every edge (rising and falling), specified edge first. 4. prescaler capture event modes - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of two 16-bit timers (timer2 or timer3) for the time base, or two 16-bit timers (timer2 and timer3) together to form a 32-bit timer. the selected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? input capture can also be used to provide additional sources of external interrupts figure 15-1: input capture block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?input capture? (ds61122) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. prescaler 1, 4, 16 edge detect fifo control interrupt event generation icxbuf<31:16> interrupt timer3 timer2 icxcon ici<1:0> icx input 0 1 icxbuf<15:0> data space interface peripheral data bus c32 ictmr icm<2:0> fedge icbne icov icm<2:0> free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 140 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 141 pic32mx5xx/6xx/7xx 16.0 output compare the output compare module (ocmp) is used to generate a single pulse or a train of pulses in response to selected time base events. for all modes of operation, the ocmp module compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the ocmp module generates an event based on the selected mode of operation. the following are some of the key features: ? multiple output compare modules in a device ? programmable interrupt generation on compare event ? single and dual compare modes ? single and continuous output pulse generation ? pulse-width modulation (pwm) mode ? hardware-based pwm fault detection and automatic output disable ? programmable selection of 16-bit or 32-bit time bases ? can operate from either of two available 16-bit time bases or a single 32-bit time base figure 16-1: output compare module block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?output compare? (ds61111) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is made to the register s associated with the respec tive output compare channels, 1 through 5. 2: the ocfa pin controls the oc1-oc4 channels. the ocfb pin controls the oc5 channel. 3: each output compare channel can use one of two selectabl e 16-bit time bases or a single 32-bit timer base. 0 1 octsel 0 1 16 16 ocfa or ocfb (2) tmr register inputs from time bases (3) period match signals from time bases (3) logic output enable free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 142 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 143 pic32mx5xx/6xx/7xx 17.0 serial peripheral interface (spi) the spi module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. these peripheral devices may be serial eeprom s, shift registers, dis- play drivers, analog-to-digital converters, etc. the pic32 spi module is compatible with motorola ? spi and siop interfaces. following are some of the key features of this module: ? master and slave modes support ? four different clock formats ? enhanced framed spi protocol support ? user-configurable 8-bit, 16-bit and 32-bit data width ? separate spi fifo buffers for receive and transmit - fifo buffers act as 4/8/16-level deep fifos based on 32/16/8-bit data width ? programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer ? operation during cpu sleep and idle mode ? fast bit manipulation using clr, set and inv registers figure 17-1: spi module block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 23. ?serial peripheral interface (spi)? (ds61106) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. internal data bus sdix sdox ssx /f sync sckx spixsr bit 0 shift control edge select enable master clock baud rate slave select sync control clock control transmit receive and frame note: access spixtxb and spixrxb fi fos via spixbuf register. fifos share address spixbuf spixbuf generator pbclk write read spixtxb fifo spixrxb fifo free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 144 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 145 pic32mx5xx/6xx/7xx 18.0 inter-integrated circuit? (i 2 c?) the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard. figure 18-1 illustrates the i 2 c module block diagram. each i 2 c module has a 2-pin interface: the sclx pin is clock and the sdax pin is data. each i 2 c module offers the following key features: ?i 2 c interface supporting both master and slave operation ?i 2 c slave mode supports 7-bit and 10-bit addressing ?i 2 c master mode supports 7-bit and 10-bit addressing ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synchronization for the i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) ?i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly ? provides support for address bit masking note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 24. ?inter- integrated circuit? (i 2 c?)? (ds61116) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 146 ? 2009-2011 microchip technology inc. figure 18-1: i 2 c? block diagram internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 147 pic32mx5xx/6xx/7xx 19.0 universal asynchronous receiver transmitter (uart) the uart module is one of the serial i/o modules available in pic32mx5xx/6xx/7xx family devices. the uart is a full-duplex, asynchronous communica- tion channel that communicates with peripheral devices and personal computers through protocols, such as rs-232, rs-485, lin 1.2 and irda ? . the module also supports the hardware flow control option, with uxcts and uxrts pins, and also includes an irda encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware auto-baud feature ? hardware flow control option ? fully integrated baud rate generator (brg) with 16-bit prescaler ? baud rates ranging from 76 bps to 20 mbps at 80 mhz ? 8-level deep first-in-first-out (fifo) transmit data buffer ? 8-level deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt-only on address detect (9th bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? lin 1.2 protocol support ? irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 19-1 illustrates a simplified block diagram of the uart. figure 19-1: uart simplified block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. ?universal asynchronous receiver transmitter (uart)? (ds61107) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts bclkx irda ? note: not all pins are available for all uart modules. refer to the device-specific pin di agram for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 148 ? 2009-2011 microchip technology inc. figure 19-2 and figure 19-3 illustrate typical receive and transmit timing for the uart module. figure 19-2: uart reception figure 19-3: transmission (8-bit or 9-bit data) start 1 stop start 2 stop 4 start 5 stop 10 start 11 stop 13 cleared by software read to uxrxreg uxrx ridle oerr uxrxif urxisel = 00 uxrxif urxisel = 01 uxrxif urxisel = 10 char 1 char 2-4 char 5-10 char 11-13 cleared by software cleared by software start start bit 0 bit 1 stop write to tsr bclk/16 (shift clock) uxtx uxtxif uxtxif utxisel = 00 bit 1 uxtxreg utxisel = 01 uxtxif utxisel = 10 8 into txbuf pull from buffer free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 149 pic32mx5xx/6xx/7xx 20.0 parallel master port (pmp) the pmp is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. figure 20-1 shows the pmp module pinout and its connections to external devices. key features of the pmp module include: ? 8-bit, 16-bit interface ? up to 16 programmable address lines ? up to two chip select lines ? programmable strobe options - individual read and write strobes, or - read/write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? parallel slave port support - legacy addressable - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? operates during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers ? freeze option for in-circuit debugging figure 20-1: pmp module pinout and connections to external devices note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?parallel master port (pmp)? (ds61128) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. note: on 64-pin devices, the pmd<15:8> data pins are not available. pma<0> pma<14> pma<15> pmrd pmwr pmenb pmrd/pmwr pmcs1 pma<1> pma<13:2> pmall pmalh pmcs2 flash address bus data bus control lines pic32mx5xx/6xx/7xx lcd fifo microcontroller 16/8-bit data (with or without multiplexed addressing) up to 16-bit address parallel buffer pmd<15:8> (1) pmd<7:0> master port note 1: on 64-pin devices, data pins, pmd<15:8>, ar e not available in 16-bit master modes. eeprom sram free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 150 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 151 pic32mx5xx/6xx/7xx 21.0 real-time clock and calendar (rtcc) the pic32 rtcc module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low-power optimization provides extended battery lifetime while keeping track of time. a simplified block diagram of the rtcc module is illustrated in figure 21-1 . following are some of the key features of this module: ? time: hours, minutes and seconds ? 24-hour format (military time) ? visibility of one-half second period ? provides calendar: weekday, date, month and year ? alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat: chime ? year range: 2000 to 2099 ? leap year correction ? bcd format for smalle r firmware overhead ? optimized for long-term battery operation ? fractional second synchronization ? user calibration of the clock crystal frequency with auto-adjust ? calibration range: 0.66 seconds error per month ? calibrates up to 260 ppm of crystal error ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on rtcc pin figure 21-1: rtcc block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. ?real-time clock and calendar (rtcc)? (ds61125) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. seconds pulse rtcc prescalers rtcc timer comparator compare registers repeat counter year, mth, day wkday hr, min, sec mth, day wkday hr, min, sec with masks rtcc interrupt logic alarm event 32.768 khz input from secondary 0.5s alarm pulse rtcc interrupt rtcval alrmval rtcc pin rtcoe oscillator (s osc ) free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 152 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 153 pic32mx5xx/6xx/7xx 22.0 10-bit analog-to-digital converter (adc) the pic32mx5xx/6xx/7xx 10-bit analog-to-digital converter (adc) includes the following features: ? successive approximation register (sar) conversion ? up to 1 msps conversion speed ? up to 16 analog input pins ? external voltage reference input pins ? one unipolar, differential sample and hold amplifier (sha) ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? eight conversion result format options ? operation during cpu sleep and idle modes a block diagram of the 10-bit adc is illustrated in figure 22-1 . the 10-bit adc has up to 16 analog input pins, designated an0-an15. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. the analog inputs are connected through two multi- plexers (muxs) to one sha. the analog input muxs can be switched between two sets of analog inputs between conversions. unipolar differential conversions are possible on all channels , other than the pin used as the reference, using a reference input pin (see figure 22-1 ). the analog input scan mode sequentially converts user-specified channels. a control register specifies which analog input channels will be included in the scanning sequence. the 10-bit adc is connected to a 16-word result buffer. each 10-bit result is converted to one of eight 32-bit output formats when it is read from the result buffer. figure 22-1: adc1 module block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?10-bit analog-to-digital converter (adc)? (ds61104) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. sar adc s/h adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0 an15 an1 v refl ch0sb<4:0> ch0na ch0nb + - ch0sa<4:0> channel scan cscna alternate v ref + (1) av dd av ss v ref - (1) note 1: v ref + and v ref - inputs can be multiplexed with other analog inputs. input selection v refh v refl vcfg<2:0> free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 154 ? 2009-2011 microchip technology inc. figure 22-2: adc conversion clock period block diagram 1 0 div 2 t pb adc conversion clock multiplier 2, 4,..., 512 adrc t ad 8 adcs<7:0> frc free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 155 pic32mx5xx/6xx/7xx 23.0 controller area network (can) the controller area network (can) module supports the following key features: ? standards compliance: - full can 2.0b compliance - programmable bit rate up to 1 mbps ? message reception and transmission: - 32 message fifos - each fifo can have up to 32 messages for a total of 1024 messages - fifo can be a transmit message fifo or a receive message fifo - user-defined priority levels for message fifos used for transmission - 32 acceptance filters for message filtering - four acceptance filter mask registers for message filtering - automatic response to remote transmit request - devicenet? addressing support ? additional features: - loopback, listen all messages and listen only modes for self-test, system diagnostics and bus monitoring - low-power operating modes - can module is a bus master on the pic32 system bus - use of dma is not required - dedicated time-stamp timer - dedicated dma channels - data-only message reception mode figure 23-1 illustrates the general structure of the can module. figure 23-1: pic32 can module block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 34. ?controller area network (can)? (ds61154) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 message buffer 31 message buffer 1 message buffer 0 fifo0 fifo1 fifo31 system ram up to 32 message buffers can message fifo (up to 32 fifos) message buffer size 2 or 4 words system bus cpu can module 32 filters 4 masks cxtx cxrx free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 156 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 157 pic32mx5xx/6xx/7xx 24.0 ethernet controller the ethernet controller is a bus master module that interfaces with an off-chip physical layer (phy) to implement a comple te ethernet node in a system. following are some of the key features of this module: ? supports 10/100 mbps data transfer rates ? supports full-duplex and half-duplex operation ? supports rmii and mii phy interface ? supports miim phy management interface ? supports both manual and automatic flow control ? ram descriptor-based dma operation for both receive and transmit path ? fully configurable interrupts ? configurable receive packet filtering - crc check - 64-byte pattern match - broadcast, multicast and unicast packets - magic packet? - 64-bit hash table - runt packet ? supports packet paylo ad checksum calculation ? supports various hardwa re statistics counters figure 24-1 illustrates a block diagram of the ethernet controller. figure 24-1: ethernet co ntroller block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 35. ?ethernet controller? (ds61155) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. tx bus master system bus rx bus master tx dma tx flow control host if rx dma rx filter checksum mac external phy mii/rmii if miim if mac control and configuration registers tx function rx function dma control registers fast peripheral bus ethernet controller rx flow control ethernet dma rx bm tx bm tx fifo rx fifo free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 158 ? 2009-2011 microchip technology inc. table 24-1 , table 24-2 , table 24-3 and ta b l e 2 4 - 4 show four interfaces and the associated pins that can be used with the ethernet controller. table 24-1: mii mode default interface signals (fmiien = 1 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxclk transmit clock etxen transmit enable etxd0 transmit data etxd1 transmit data etxd2 transmit data etxd3 transmit data etxerr transmit error erxclk receive clock erxdv receive data valid erxd0 receive data erxd1 receive data erxd2 receive data erxd3 receive data erxerr receive error ecrs carrier sense ecol collision indication table 24-2: rmii mode default interface signals (fmiien = 0 , fethio = 1 ) pin name description emdc management clock emdio management i/o etxen transmit enable etxd0 transmit data etxd1 transmit data erefclk reference clock ecrsdv carrier sense ? receive data valid erxd0 receive data erxd1 receive data erxerr receive error note: ethernet controller pins that are not used by selected interface can be used by other peripherals. table 24-3: mii mode alternate interface signals (fmiien = 1 , fethio = 0 ) (1) pin name description aemdc management clock aemdio management i/o aetxclk transmit clock aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aetxd2 transmit data aetxd3 transmit data aetxerr transmit error aerxclk receive clock aerxdv receive data valid aerxd0 receive data aerxd1 receive data aerxd2 receive data aerxd3 receive data aerxerr receive error aecrs carrier sense aecol collision indication note 1: mii alternate interface is not available on 64-pin devices. table 24-4: rmii mode alternate interface signals (fmiien = 0 , fethio = 0 ) pin name description aemdc management clock aemdio management i/o aetxen transmit enable aetxd0 transmit data aetxd1 transmit data aerefclk reference clock aecrsdv carrier sense ? receive data valid aerxd0 receive data aerxd1 receive data aerxerr receive error free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 159 pic32mx5xx/6xx/7xx 25.0 comparator the analog comparator module contains two compar- ators that can be configured in a variety of ways. following are some of the key features of this module: ? selectable inputs available include: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference (iv ref ) - comparator voltage reference (cv ref ) ? outputs can be inverted ? selectable interrupt generation a block diagram of the comparator module is illustrated in figure 25-1 . figure 25-1: comparator block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?comparator? (ds61110) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. c1 cv ref (2) c1in+ (1) c1in+ c1in- c1out cout (cm1con<8>) cref cch<1:0> cpol coe on c2in+ iv ref (2) c1out (cmstat<0>) c2 cv ref (2) c2in+ c2in+ c2in- c2out cout (cm2con<8>) cref cpol coe on c1in+ iv ref (2) c2out (cmstat<1>) comparator 2 comparator 1 cch<1:0> note 1: on devices with a usb module, and when the module is e nabled, this pin is controlled by the usb module, and therefore, is not available as a comparator input. 2: internally connected. see section 26.0 ?comparator voltage reference (cv ref )? . free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 160 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 161 pic32mx5xx/6xx/7xx 26.0 comparator voltage reference (cv ref ) the cv ref module is a 16-tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. a block diagram of the module is illustrated in figure 26-1 . the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. the module?s supply refer- ence can be provided from either device v dd /v ss or an external voltage reference. the cv ref output is avail- able for the comparators and typically available for pin output. the comparator voltage reference has the following features: ? high and low range selection ? sixteen output levels available for each range ? internally connected to comparators to conserve device pins ? output can be connected to a pin figure 26-1: comparator voltage reference block diagram note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 20. ?comparator voltage reference (cv ref )? (ds61109) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32) . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv refout av ss cvroe (cvrcon<6>) cv ref v refsel (1) iv ref 1.2v 0.6v bgsel<1:0> (1) note 1: this bit is not available on pic32mx 575/675/695/775 devices. on these devices cv ref is generated by the register network and iv ref is connected to 0.6v. cv rsrc free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 162 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 163 pic32mx5xx/6xx/7xx 27.0 power-saving features this section describes power-saving features for the pic32mx5xx/6xx/7xx family of devices. these devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumpti on with device performance. in all of the methods and modes described in this section, power-saving is controlled by software. 27.1 power-saving with cpu running when the cpu is running, power consumption can be controlled by reducing the cpu clock frequency, lowering the pbclk and by individually disabling modules. these methods are grouped into the following categories: ? frc run mode: the cpu is clocked from the frc clock source with or without postscalers. ? lprc run mode: the cpu is clocked from the lprc clock source. ?s osc run mode: the cpu is clocked from the s osc clock source. in addition, the peripheral bus scaling mode is available where peripherals are clocked at the programmable fraction of the cpu clock (sysclk). 27.2 cpu halted methods the device supports two power-saving modes, sleep and idle, both of which halt the clock to the cpu. these modes operate with all clock sources, as listed below: ?p osc idle mode: the system clock is derived from the p osc . the system clock source continues to operate. peripherals continue to operate, but can optionally be individually disabled. ? frc idle mode: the system clock is derived from the frc with or without postscalers. peripherals continue to operate, but can optionally be individually disabled. ?s osc idle mode: the system clock is derived from the s osc . peripherals continue to operate, but can optionally be individually disabled. ? lprc idle mode: the system clock is derived from the lprc. peripherals continue to operate, but can optionally be individually disabled. this is the lowest power mode for th e device with a clock running. ? sleep mode: the cpu, the system clock source and any peripherals that operate from the system clock source are halted. some peripherals can operate in sleep using specific clock sources. this is the lowest power mode for the device. 27.3 power-saving operation peripherals and the cpu can be halted or disabled to further reduce power consumption. 27.3.1 sleep mode sleep mode has the lowest power consumption of the device power-saving operating modes. the cpu and most peripherals are halted. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: ? the cpu is halted ? the system clock source is typically shutdown. see section 27.3.3 ?peripheral bus scaling method? for specific information. ? there can be a wake-up delay based on the oscillator selection ? the fail-safe clock monitor (fscm) does not operate during sleep mode ? the bor circuit, if enabled, remains operative during sleep mode ? the wdt, if enabled, is not automatically cleared prior to entering sleep mode ? some peripherals can continue to operate at limited functionality in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart and peripherals that use an external clock input or the internal lprc oscillator (e.g., rtcc, timer1 and input capture). ? i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep ? modules can be individually disabled by software prior to entering sleep in order to further reduce consumption note 1: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. ?power- saving features? (ds61130) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for device-specific register and bit information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 164 ? 2009-2011 microchip technology inc. the processor will exit, or ?wake-up?, from sleep on one of the following events: ? on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. ? on any form of device reset ? on a wdt time-out if the interrupt priority is lower than or equal to the current priority, the cpu will remain halted, but the pbclk will start running and the device will enter into idle mode. 27.3.2 idle mode in idle mode, the cpu is halted but the system clock (sysclk) source is still enabled. this allows peripher- als to continue operation when the cpu is halted. peripherals can be individually configured to halt when entering idle by setting their respective sidl bit. latency, when exiting idle mode, is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen bit (osccon<4>) is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: ? on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of the cpu. if the priority of the interrupt event is lower than or equal to current priority of the cpu, the cpu will remain halted and the device will remain in idle mode. ? on any form of device reset ? on a wdt time-out interrupt 27.3.3 peripheral bus scaling method most of the peripherals on the device are clocked using the pbclk. the peripheral bus can be scaled relative to the sysclk to minimize the dynamic power consumed by the peripherals. the pbcl k divisor is controlled by pbdiv<1:0> (osccon<20:19>), allowing sysclk to pbclk ratios of 1:1, 1:2, 1:4 and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as usb, interrupt controller, dma, bus matrix and prefetch cache are clocked directly from sysclk. as a result, they are not affected by pbclk divisor changes. changing the pbclk divisor affects: ? the cpu to peripheral access latency. the cpu has to wait for next pbclk edge for a read to complete. in 1:8 mode, this results in a latency of one to seven sysclks. ? the power consumption of the peripherals. power consumption is directly proportional to the fre- quency at which the peripherals are clocked. the greater the divisor, the lower the power consumed by the peripherals. to minimize dynamic power, the pb divisor should be chosen to run the peripherals at the lowest frequency that provides acceptabl e system performance. when selecting a pbclk divider, peripheral clock require- ments, such as baud rate accuracy, should be taken into account. for example, the uart peripheral may not be able to achieve all baud rate values at some pbclk divider depending on the sysclk value. note 1: changing the pbclk divider ratio requires recalculation of peripheral tim- ing. for example, assume the uart is configured for 9600 baud with a pb clock ratio of 1:1 and a p osc of 8 mhz. when the pb clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. for this reason, any timing cal- culation required for a peripheral should be performed with the new pb clock fre- quency instead of scaling the previous value based on a change in the pb divisor ratio. 2: oscillator start-up and pll lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the pll. for example, assume the clock source is switched from p osc to lprc just prior to entering sleep in order to save power. no oscillator start- up delay would be applied when exiting idle. however, when switching back to p osc , the appropriate pll and/or oscillator start-up/lock delays would be applied. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 165 pic32mx5xx/6xx/7xx 28.0 special features pic32mx5xx/6xx/7xx devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. these are: ? flexible device configuration ? watchdog timer (wdt) ? joint test action group (jtag) interface ? in-circuit serial programming? (icsp?) 28.1 configuration bits the configuration bits can be programmed using the following registers to select various device configurations. ? devcfg0: device configuration word 0 ? devcfg1: device configuration word 1 ? devcfg2: device configuration word 2 ? devcfg3: device configuration word 3 ? devid: device and revision id register note: this data sheet summarizes the features of the pic32mx5xx/6xx/7xx family of devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?watchdog timer and power-up timer? (ds61114), section 24. ?configuration? (ds61124) and section 33. ?programming and diagnostics? (ds61129) in the ?pic32 family reference manual? (ds61132), which is available from the microchip web site ( www.microchip.com/pic32 ). free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 166 ? 2009-2011 microchip technology inc. register 28-1: devcfg0: d evice configuration word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r/p r-1 r-1 r-1 r/p ? ? ?cp ? ? ?bwp 23:16 r-1 r-1 r-1 r-1 r/p r/p r/p r/p ? ? ? ? pwp<7:4> 15:8 r/p r/p r/p r/p r-1 r-1 r-1 r-1 pwp<3:0> ? ? ? ? 7:0 r-1 r-1 r-1 r-1 r/p r-1 r/p r/p ? ? ? ? icesel ? debug<1:0> legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 reserved: write ? 0 ? bit 30-29 reserved: write ? 1 ? bit 28 cp: code-protect bit prevents boot and program flash memory from being read or modified by an external programming device. 1 = protection is disabled 0 = protection is enabled bit 27-25 reserved: write ? 1 ? bit 24 bwp: boot flash write-protect bit prevents boot flash memory from being modified during code execution. 1 = boot flash is writable 0 = boot flash is not writable bit 23-20 reserved: write ? 1 ? bit 19-12 pwp<7:0>: program flash write-protect bits prevents selected program flash memory pages from being modified during code execution. the pwp bits represent the 1?s complement of the number of write-protected program flash memory pages. 11111111 = disabled 11111110 = 0xbd00_0fff 11111101 = 0xbd00_1fff 11111100 = 0xbd00_2fff 11111011 = 0xbd00_3fff 11111010 = 0xbd00_4fff 11111001 = 0xbd00_5fff 11111000 = 0xbd00_6fff 11110111 = 0xbd00_7fff 11110110 = 0xbd00_8fff 11110101 = 0xbd00_9fff 11110100 = 0xbd00_afff 11110011 = 0xbd00_bfff 11110010 = 0xbd00_cfff 11110001 = 0xbd00_dfff 11110000 = 0xbd00_efff 11101111 = 0xbd00_ffff ? ? ? 01111111 = 0xbd07_ffff free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 167 pic32mx5xx/6xx/7xx bit 11-4 reserved: write ? 1 ? bit 3 icesel: in-circuit emulator/debugger communication channel select bit 1 = pgec2/pged2 pair is used 0 = pgec1/pged1 pair is used bit 2 reserved: write ? 1 ? bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 11 = debugger is disabled 10 = debugger is enabled 01 = reserved (same as ? 11 ? setting) 00 = reserved (same as ? 11 ? setting) register 28-1: devcfg0: device configuration word 0 (continued) free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 168 ? 2009-2011 microchip technology inc. register 28-2: devcfg1: d evice configuration word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r/p r-1 r-1 r/p r/p r/p r/p r/p fwdten ? ? wdtps<4:0> 15:8 r/p r/p r/p r/p r-1 r/p r/p r/p fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> 7:0 r/p r-1 r/p r-1 r-1 r/p r/p r/p ieso ? fsoscen ? ?fnosc<2:0> legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 reserved: write ? 1 ? bit 23 fwdten: watchdog timer enable bit 1 = the wdt is enabled and cannot be disabled by software 0 = the wdt is not enabled; it can be enabled in software bit 22-21 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = 10100 bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 169 pic32mx5xx/6xx/7xx bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output disabled 0 = clko output signal active on the osco pin; primar y oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmod<1:0> = 11 or 00 ) bit 9-8 poscmod<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdiv) 110 = frcdiv16 fast rc oscillator with fixed divide-by-16 postscaler 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xt+pll, hs+pll, ec+pll) 010 = primary oscillator (xt, hs, ec) (1) 001 = fast rc oscillator with divi de-by-n with pll module (frcdiv+pll) 000 = fast rc oscillator (frc) register 28-2: devcfg1: device configuration word 1 (continued) note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 170 ? 2009-2011 microchip technology inc. register 28-3: devcfg2: d evice configuration word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fpllodiv<2:0> 15:8 r/p r-1 r-1 r-1 r-1 r/p r/p r/p upllen ? ? ? ? upllidiv<2:0> 7:0 r-1 r/p-1 r/p r/p-1 r-1 r/p r/p r/p ? fpllmul<2:0> ? fpllidiv<2:0> legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-19 reserved: write ? 1 ? bit 18-16 fpllodiv<2:0>: default postscaler for pll bits 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 15 upllen: usb pll enable bit 1 = disable and bypass usb pll 0 = enable usb pll bit 14-11 reserved: write ? 1 ? bit 10-8 upllidiv<2:0>: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 reserved: write ? 1 ? bit 6-4 fpllmul<2:0>: pll multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 reserved: write ? 1 ? bit 2-0 fpllidiv<2:0>: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 171 pic32mx5xx/6xx/7xx register 28-4: devcfg3: d evice configuration word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r-1 r-1 r-1 r/p r/p r/p fvbusonio fusbidio ? ? ? fcanio (1) fethio (2) fmiien (2) 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fsrssel<2:0> 15:8 r/p r/p r/p r/p r/p r/p r/p r/p userid<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p userid<7:0> legend: r = readable bit w = writable bit p = programmable bit r = reserved bit u = unimplemented bit ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 fvbusonio: usb vbus_on selection bit 1 = vb uson pin is controlled by the usb module 0 = vb uson pin is controlled by the port function bit 30 fusbidio: usb usbid selection bit 1 = usbid pin is controlled by the usb module 0 = usbid pin is controlled by the port function bit 29-27 reserved: write ? 1 ? bit 26 fcanio: can i/o pin selection bit (1) 1 = default can i/o pins 0 = alternate can i/o pins bit 25 fethio: ethernet i/o pin selection bit (2) 1 = default ethernet i/o pins 0 = alternate ethernet i/o pins bit 24 fmiien: ethernet mii enable bit (2) 1 = mii is enabled 0 = rmii is enabled bit 23-19 reserved: write ? 1 ? bit 18-16 fsrssel<2:0>: srs select bits 111 = assign interrupt priority 7 to a shadow register set 110 = assign interrupt priority 6 to a shadow register set ? ? ? 001 = assign interrupt priority 1 to a shadow register set 000 = all interrupt priorities are assigned to a shadow register set bit 15-0 userid<15:0>: this is a 16-bit value that is user-defined and is readable via icsp? and jtag note 1: this bit is reserved and reads ? 1 ? on pic32mx664/675/695 devices. 2: this bit is reserved and reads ? 1 ? on pic32mx534/564/575 devices. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 172 ? 2009-2011 microchip technology inc. register 28-5: devid: device and revision id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrrrrr ver<3:0> (1) devid<27:24> (1) 23:16 rrrrrrrr devid<23:16> (1) 15:8 rrrrrrrr devid<15:8> (1) 7:0 rrrrrrrr devid<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 ver<3:0>: revision identifier bits (1) bit 27-0 devid<27:0>: device id (1) note 1: see the ?pic32 flash programming specification? (ds61145) for a list of revision and device id values. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 173 pic32mx5xx/6xx/7xx 28.2 watchdog timer (wdt) this section describes the operation of the wdt and power-up timer of the pic32mx5xx/6xx/7xx. the wdt, when enabled, operates from the internal low-power oscillator (lprc) clock source and can be used to detect system software malfunctions by reset- ting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. the following are some of the key features of the wdt module: ? configuration or software controlled ? user-configurable time-out period ? can wake the device from sleep or idle figure 28-1: watchdog and power-up timer block diagram wake wdtclr = 1 wdt enable lprc power save 25-bit counter pwrt enable wdt enable lprc wdt counter reset control oscillator 25 device reset nmi (wake-up) pwrt pwrt enable fwdtps<4:0> (devcfg1<20:16>) clock decoder 1 1:64 output 0 1 wdt enable reset event free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 174 ? 2009-2011 microchip technology inc. 28.3 on-chip voltage regulator all pic32mx5xx/6xx/7xx devi ces? core and digital logic are designed to operate at a nominal 1.8v. to simplify system designs, most devices in the pic32mx5xx/6xx/7xx family incorporate an on-chip regulator providing the required core logic voltage from v dd . a low-esr capacitor (such as tantalum) must be connected to the v cap /v core pin (see figure 28-2 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 31.1 ?dc characteristics? . 28.3.1 on-chip regulator and por it takes a fixed delay for the on-chip regulator to generate an output. during this time, designated as t pu , code execution is disabled. t pu is applied every time the device resumes operation after any power-down, including sleep mode. 28.3.2 on-chip regulator and bor pic32mx5xx/6xx/7xx devi ces also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specified in section 31.1 ?dc characteristics? . 28.3.3 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, strict power-up conditions must be adhered to. while powering up, v core must never exceed v dd by 0.3v. figure 28-2: connections for the on-chip regulator note: it is important that the low-esr capacitor is placed as close as possible to the v cap /v core pin. v dd v cap /v core v ss pic32 c efc (2) 3.3v (1) note 1: these are typical operating voltages. refer to section 31.1 ?dc characteristics? for the full operating ranges of v dd and v core . 2: it is important that the low-esr capacitor is placed as close as possible to the v cap /v core pin. (10 f typ) free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 175 pic32mx5xx/6xx/7xx 28.4 programming and diagnostics pic32mx5xx/6xx/7xx devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. these features allow system desig ners to include: ? simplified field programmability using two-wire in-circuit serial programming? (icsp?) interfaces ? debugging using icsp ? programming and debugging capabilities using the ejtag extension of jtag ? jtag boundary scan testing for device and board diagnostics pic32 devices incorporate two programming and diag- nostic modules, and a trace controller, that provide a range of functions to the application developer. figure 28-3: block diagram of programming, debugging and trace ports tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> instruction trace controller debug<1:0> icesel pgec1 pged1 pgec2 pged2 trclk trd0 trd1 trd2 trd3 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 176 ? 2009-2011 microchip technology inc. register 28-6: ddpcon: debug data port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 u-0 r/w-0 ? ? ? ?jtagentroen ?tdoen legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 jtagen: jtag port enable bit 1 = enable the jtag port 0 = disable the jtag port bit 2 troen: trace output enable bit 1 = enable the trace port 0 = disable the trace port bit 1 unimplemented: read as ? 0 ? bit 0 tdoen: tdo enable for 2-wire jtag 1 = 2-wire jtag protocol uses tdo 0 = 2-wire jtag protocol does not use tdo free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 177 pic32mx5xx/6xx/7xx 29.0 instruction set the pic32mx5xx/6xx/7xx fa mily instruction set complies with the mips32 release 2 instruction set architecture. the pic32 device family does not support the following features: ? core extend instructions ? coprocessor 1 instructions ? coprocessor 2 instructions note: refer to ?mips32 ? architecture for programmers volume ii: the mips32 ? instruction set? at www.mips.com for more information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 178 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 179 pic32mx5xx/6xx/7xx 30.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 30.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 180 ? 2009-2011 microchip technology inc. 30.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 30.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 30.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 30.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 181 pic32mx5xx/6xx/7xx 30.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 30.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-sp eed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 30.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 30.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and programming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 182 ? 2009-2011 microchip technology inc. 30.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use interface for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcontrollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a breakpoint, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 30.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices wi thout a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 30.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 183 pic32mx5xx/6xx/7xx 31.0 electrical characteristics this section provides an overview of the pic32mx5xx/6xx/7xx electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic32mx5xx/6xx/7xx devices are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings (note 1) ambient temperature under bias................................................................................................. ............-40c to +105c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (note 3) ......................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd 2.3v (note 3) ........................................ -0.3v to +5.5v voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v (note 3) ........................................ -0.3v to +3.6v voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v voltage on v core with respect to v ss ....................................................................................................... -0.3v to 2.0v maximum current out of v ss pin(s) .......................................................................................................................3 00 ma maximum current into v dd pin(s) (note 2) ............................................................................................................300 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (note 2) ....................................................................................................200 ma note 1: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional op eration of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 31-2 ). 3: see the ? pin diagrams ? section for the 5v tolerant pins. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 184 ? 2009-2011 microchip technology inc. 31.1 dc characteristics table 31-1: operating mips vs. voltage characteristic v dd range (in volts) temp. range (in c) max. frequency pic32mx5xx/6xx/7xx dc5 2.3-3.6v -40c to +85c 80 mhz dc5b 2.3-3.6v -40c to +105c 80 mhz table 31-2: thermal operating conditions rating symbol min. typical max. unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c v-temp temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +105 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? s i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = s (({v dd ? v oh } x i oh ) + s (v ol x i ol )) maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 31-3: thermal packaging characteristics characteristics symbol typical max. unit see note package thermal resistance, 121-pin xbga (10x10x1.1 mm) ja 40 ? c/w 1 package thermal resistance, 100-pin tqfp (14x14x1 mm) ja 43 ? c/w 1 package thermal resistance, 100-pin tqfp (12x12x1 mm) ja 43 ? c/w 1 package thermal resistance, 64-pin tqfp (10x10x1 mm) ja 47 ? c/w 1 package thermal resistance, 64-pin qfn (9x9x0.9 mm) ja 28 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. table 31-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions operating voltage dc10 v dd supply voltage 2.3 ? 3.6 v ? dc12 v dr ram data retention voltage (1) 1.75 ? ? v ? dc16 v por v dd start voltage to ensure internal power-on reset signal 1.75 ? 2.1 v ? dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.00005 ? 0.115 v/ s? note 1: this is the limit to which v dd can be lowered without losing ram data. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 185 pic32mx5xx/6xx/7xx table 31-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. typical (3) max. units conditions operating current (i dd ) (1,2) for pic32mx575/675/695/775 family devices dc20 6 9 ma code executing from flash -40oc, +25oc, +85oc ?4 mhz dc20b 7 10 +105oc dc20a 4 ? code executing from sram ? dc21 37 40 ma code executing from flash ?? 25 mhz (note 4) dc21a 25 ? code executing from sram dc22 64 70 ma code executing from flash ?? 60 mhz (note 4) dc22a 61 ? code executing from sram dc23 85 98 ma code executing from flash -40oc, +25oc, +85oc ?80 mhz dc23b 90 120 +105oc dc23a 85 ? code executing from sram ? dc25a 125 150 a ? +25c 3.3v lprc (31 khz) (note 4) operating current (i dd ) (1,2,5) for pic32mx534/564/66 4/764 family devices dc20b 6 9 ma code executing from flash ? ? 4 mhz dc20c 2 ? ma code executing from sram ? ? dc21b 19 40 ma code executing from flash ? ? 25 mhz (note 4) dc21c 14 ? ma code executing from sram ? ? dc22b 31 70 ma code executing from flash ? ? 60 mhz (note 4) dc22c 29 ? ma code executing from sram ? ? dc23b 39 98 ma code executing from flash ? ? 80 mhz dc23c 39 ? ma code executing from sram ? ? dc25b 100 150 a ? +25c 3.3v lprc (31 khz) (note 4) note 1: a device?s i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, num ber of peripheral modules enabled, internal code execution pattern, execution from program flash memory vs. sram, i/o pin loading and switching rate, oscillator type, as well as temperature, c an have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: oscillator mode = ec+pll with osc1 driven by external square wave from rail-to-rail and pbclk divisor = 1:8. cpu, program flash and sram data memory are operational, program flash memory wait states = 7, program cache and prefetch are dis- abled and sram data memory wait states = 1 . all peripheral modules are disabled (on bit = 0 ). wdt and fscm are disabled. all i/o pins are configured as inputs and pulled to v ss . mclr = v dd . 3: data in ?typical? column is at 3.3v, 25c at specified operating frequency unless otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing. 5: this information is preliminary. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 186 ? 2009-2011 microchip technology inc. table 31-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp parameter no. typical (2) max. units conditions idle current (i idle ): core off, clock on base current (1) for pic32mx575/675/695/775 family devices dc30 4.5 6.5 ma -40oc, +25oc, +85oc ?4 mhz dc30b 5 7 ma +105c dc31 13 15 ma -40oc, +25oc, +85oc ? 25 mhz (note 3) dc32 28 30 ma -40oc, +25oc, +85oc ? 60 mhz (note 3) dc33 36 42 ma -40oc, +25oc, +85oc ?80 mhz dc33b 39 45 ma +105c dc34 ? 40 a -40c 2.3v lprc (31 khz) (note 3) dc34a ? 75 a +25c dc34b ? 800 a +85c dc34c ? 1000 a +105c dc35 35 ? a -40c 3.3v dc35a 65 ? a +25c dc35b 600 ? a +85c dc35c 800 ? a +105c dc36 ? 43 a -40c 3.6v dc36a ? 106 a +25c dc36b ? 800 a +85c dc36c ? 1000 a +105c idle current (i idle ): core off, clock on base current (1,4) for pic32mx534/564/664/764 family devices dc30a 1.5 6.5 ma -40oc, +25oc, +85oc ? 4 mhz dc31a 7 15 ma -40oc, +25oc, +85oc ? 25 mhz (note 3) dc32a 13 30 ma -40oc, +25oc, +85oc ? 60 mhz (note 3) dc33a 17 42 ma -40oc, +25oc, +85oc ? 80 mhz dc34c ? 40 a -40c 2.3v lprc (31 khz) (note 3) dc34d ? 75 a +25c dc34e ? 800 a +85c dc35c 30 ? a -40c 3.3v dc35d 55 ? a +25c dc35e 230 ? a +85c dc36c ? 43 a -40c 3.6v dc36d ? 106 a +25c dc36e ? 800 a +85c note 1: the test conditions for base i dle current measurements are as follows: system clock is enabled and pbclk divisor = 1:8. cpu in idle mode (cpu core halted). only digital peripheral modules are enabled (on bit = 1 ) and being clocked. wdt and fscm are disabled. all i/o pins are configured as inputs and pulled to v ss . mclr = v dd . 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing. 4: this information is preliminary. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 187 pic32mx5xx/6xx/7xx table 31-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. typical (2) max. units conditions power-down current (i pd ) (1) for pic32mx575/675/6 95/775 family devices dc40 10 40 a-40c 2.3v base power-down current (note 6) dc40a 36 100 a +25c dc40b 400 720 a +85c dc40h 900 1800 a +105c dc40c 41 120 a +25c 3.3v base power-down current dc40d 22 80 a-40c 3.6v base power-down current dc40e 42 120 a +25c dc40g 315 400 (5) a +70c dc40f 410 800 a +85c dc40i 1000 2000 a +105c module differential current for pi c32mx575/675/695/775 family devices dc41 ? 10 a ? 2.3v watchdog timer current: i wdt (notes 3,6) dc41a 5 ? a ? 3.3v watchdog timer current: i wdt (note 3) dc41b ? 20 a ? 3.6v watchdog timer current: i wdt (note 3) dc42 ? 40 a ? 2.3v rtcc + timer1 w/32 khz crystal: i rtcc (notes 3,6) dc42a 23 ? a ? 3.3v rtcc + timer1 w/32 khz crystal: i rtcc (note 3) dc42b ? 50 a ? 3.6v rtcc + timer1 w/32 khz crystal: i rtcc (note 3) dc43 ? 1300 a ? 2.5v adc: i adc (notes 3,4,6) dc43a 1100 ? a ? 3.3v adc: i adc (notes 3,4) dc43b ? 1300 a ? 3.6v adc: i adc (notes 3,4) power-down current (i pd ) (1,7) for pic32mx534/564/ 664/764 family devices dc40g 12 40 a-40c 2.3v base power-down current (note 6) dc40h 20 100 a +25c dc40i 210 720 a +85c dc40j 20 120 a +25c 3.3v base power-down current dc40k 15 80 a-40c 3.6v base power-down current dc40l 20 120 a +25c dc40m 113 400 (5) a +70c dc40n 210 800 a +85c note 1: base i pd is measured with all digital peripheral modules and being clocked, cpu clock is disabled. all i/os are configured as inputs and pulled low. wdt and fscm are disabled. 2: data in the ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current are as follows: internal adc rc oscillator enabled. 5: data is characterized at +70c and not tested. parameter is for design guidance only. 6: this parameter is characterized, but not tested in manufacturing. 7: this information is preliminary. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 188 ? 2009-2011 microchip technology inc. module differential current (7) for pic32mx534/564/ 664/764 family devices dc41c ? 10 a ? 2.5v watchdog timer current: i wdt (notes 3,6) dc41d 5 ? a ? 3.3v watchdog timer current: i wdt (note 3) dc41e ? 20 a ? 3.6v watchdog timer current: i wdt (note 3) dc42c ? 40 a ? 2.5v rtcc + timer1 w/32 khz crystal: i rtcc (notes 3,6) dc42d 23 ? a ? 3.3v rtcc + timer1 w/32 khz crystal: i rtcc (note 3) dc42e ? 50 a ? 3.6v rtcc + timer1 w/32 khz crystal: i rtcc (note 3) dc43c ? 1300 a ? 2.5v adc: i adc (notes 3,4,6) dc43d 1100 ? a ? 3.3v adc: i adc (notes 3,4) dc43e ? 1300 a ? 3.6v adc: i adc (notes 3,4) table 31-7: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. typical (2) max. units conditions note 1: base i pd is measured with all digital peripheral modules and being clocked, cpu clock is disabled. all i/os are configured as inputs and pulled low. wdt and fscm are disabled. 2: data in the ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current are as follows: internal adc rc oscillator enabled. 5: data is characterized at +70c and not tested. parameter is for design guidance only. 6: this parameter is characterized, but not tested in manufacturing. 7: this information is preliminary. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 189 pic32mx5xx/6xx/7xx table 31-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1 ) max. units conditions v il input low voltage di10 i/o pins: with ttl buffer v ss ?0.15v dd v with schmitt trigger buffer v ss ?0.2v dd v di15 mclr (2) v ss ?0.2v dd v di16 osc1 (xt mode) v ss ?0.2v dd v (note 4) di17 osc1 (hs mode) v ss ?0.2v dd v (note 4) di18 sdax, sclx v ss ?0.3v dd v smbus disabled (note 4) di19 sdax, sclx v ss ? 0.8 v smbus enabled (note 4) v ih input high voltage di20 i/o pins: with analog functions 0.8 v dd ?v dd v (note 4) digital only 0.8 v dd ?v with ttl buffer 0.25 v dd + 0.8v ? 5.5 v (note 4) with schmitt trigger buffer 0.8 v dd ?5.5v di25 mclr (2) 0.8 v dd ?v dd v di26 osc1 (xt mode) 0.7 v dd ?v dd v (note 4) di27 osc1 (hs mode) 0.7 v dd ?v dd v (note 4) di28 sdax, sclx 0.7 v dd ? 5.5 v smbus disabled (note 4) di29 sdax, sclx 2.1 ? 5.5 v smbus enabled, 2.3v v pin 5.5 (note 4) di30 i cnpu cnxx pull up current 50 250 400 av dd = 3.3v, v pin = v ss i il input leakage current (3) di50 i/o ports ? ? + 1 av ss v pin v dd , pin at high-impedance di51 analog input pins ? ? + 1 av ss v pin v dd , pin at high-impedance di55 mclr (2) ??+ 1 av ss v pin v dd di56 osc1 ? ? + 1 av ss v pin v dd , xt and hs modes note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 190 ? 2009-2011 microchip technology inc. table 31-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions v ol output low voltage do10 i/o ports ? ? 0.4 v i ol = 7 ma, v dd = 3.6v ??0.4vi ol = 6 ma, v dd = 2.3v do16 osc2/clko ? ? 0.4 v i ol = 3.5 ma, v dd = 3.6v ??0.4vi ol = 2.5 ma, v dd = 2.3v v oh output high voltage do20 i/o ports 2.4 ? ? v i oh = -12 ma, v dd = 3.6v 1.4 ? ? v i oh = -12 ma, v dd = 2.3v do26 osc2/clko 2.4 ? ? v i oh = -12 ma, v dd = 3.6v 1.4 ? ? v i oh = -12 ma, v dd = 2.3v table 31-10: electrical characteristics: bor dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. (1) typical max. units conditions bo10 v bor bor event on v dd transition high-to-low 2.0 ? 2.3 v ? note 1: parameters are for design guidance only and are not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 191 pic32mx5xx/6xx/7xx table 31-11: dc characteristics: program memory (3) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions program flash memory d130 e p cell endurance 1000 ? ? e/w ? d130a e p cell endurance 20,000 ? ? e/w see note 4 d131 v pr v dd for read 2.3 ? 3.6 v ? d132 v pew v dd for erase or write 3.0 ? 3.6 v ? d132a v pew v dd for erase or write 2.3 ? 3.6 v see note 4 d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10 ?ma ? t ww word write cycle time 20 ? 40 s? d136 t rw row write cycle time (2) (128 words per row) 34.5?ms ? d137 t pe page erase cycle time 20 ? ? ms ? t ce chip erase cycle time 80 ? ? ms ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the minimum sysclk for row programming is 4 mhz. care should be taken to mi nimize bus activities during row programming, such as suspending any memory-to-memory dma operations. if heavy bus loads are expected, selecting bus matrix arbitration mode 2 (rotating priority) may be necessary. the default arbitration mode is mode 1 (cpu has lowest priority). 3: refer to ?pic32 flash programming specification? (ds61145) for operating conditions during programming and erase cycles. 4: this parameter applies to pic32mx534/564/664/764 devices only. this information is preliminary. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 192 ? 2009-2011 microchip technology inc. table 31-12: program flash memory wait state characteristics dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp required flash wait states sysclk units comments 0 wait state 0 to 30 mhz ? 1 wait state 31 to 60 2 wait states 61 to 80 table 31-13: comparator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage ? 7.5 25 mv a vdd = v dd , a vss = v ss d301 v icm input common mode voltage 0 ? v dd va vdd = v dd , a vss = v ss (note 2) d302 cmrr common mode rejection ratio 55 ? ? db max v icm = (v dd - 1)v (note 2) d303 t resp response time ? 150 400 ns av dd = v dd , av ss = v ss (notes 1, 2) d304 on2 ov comparator enabled to output valid ??10 s comparator module is configured before setting the comparator on bit (note 2) d305 iv ref internal voltage reference 0.57 0.6 0.63 v for devices without bgsel<1:0> 1.14 1.2 1.26 v bgsel<1:0> = 00 0.57 0.6 0.63 v bgsel<1:0> = 01 note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . 2: these parameters are characterized but not tested. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 193 pic32mx5xx/6xx/7xx table 31-14: voltage reference specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units comments d310 v res resolution v dd /24 ? v dd /32 lsb ? d311 vr aa absolute accuracy ? ? 1/2 lsb ? d312 t set settling time (1) ? ? 10 s? d313 v iref internal voltage reference ? 0.6 ? v ? note 1: settling time measured while cvrr = 1 and cvr<3:0> transitions from ? 0000 ? to ? 1111 ?. this parameter is characterized, but not tested in manufacturing. table 31-15: internal voltage regulator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units comments d320 v core regulator output voltage 1.62 1.80 1.98 v ? d321 c efc external filter capacitor value 8 10 ? f capacitor must be low series resistance (1 ohm) d322 t pwrt power-up timer period ? 64 ? ms ? free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 194 ? 2009-2011 microchip technology inc. 31.2 ac characteristics and timing parameters the information contained in this section defines pic32mx5xx/6xx/7xx ac characteristics and timing parameters. figure 31-1: load conditions for device timing specifications figure 31-2: external clock timing v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins 50 pf for osc2 pin (ec mode) load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 table 31-16: capacitive loading requirements on output pins ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. osc1 os20 os30 os30 os31 os31 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 195 pic32mx5xx/6xx/7xx table 31-17: external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions os10 f osc external clki frequency (external clocks allowed only in ec and ecpll modes) dc 4 ? ? 50 50 mhz mhz ec (note 4) ecpll (note 3) os11 oscillator crystal frequency 3 ? 10 mhz xt (note 4) os12 4 ? 10 mhz xtpll (notes 3,4) os13 10 ? 25 mhz hs (note 5) os14 10 ? 25 mhz hspll (notes 3,4) os15 32 32.768 100 khz s osc (note 4) os20 t osc t osc = 1/f osc = t cy (2) ? ? ? ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) high or low time 0.45 x t osc ??nsec (note 4) os31 t os r, t os f external clock in (osc1) rise or fall time ? ? 0.05 x t osc ns ec (note 4) os40 t ost oscillator start-up timer period (only applies to hs, hspll, xt, xtpll and s osc clock oscillator modes) ?1024?t osc (note 4) os41 t fscm primary clock fail safe time-out period ?2?ms (note 4) os42 g m external oscillator transconductance ?12?ma/vv dd = 3.3v, t a = +25c (note 4) note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are characterized but are not tested. 2: instruction cycle period (t cy ) equals the input oscillator time base per iod. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. 3: pll input requirements: 4 mh z f pllin 5 mh z (use pll prescaler to reduce f osc ). this parameter is characterized, but tested at 10 mhz only at manufacturing. 4: this parameter is characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 196 ? 2009-2011 microchip technology inc. table 31-18: pll clock timing specifications (v dd = 2.3v to 3.6v) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 4 ? 5 mhz ecpll, hspll, xtpll, frcpll modes os51 f sys on-chip vco system frequency 60 ? 120 mhz ? os52 t lock pll start-up time (lock time) ? ? 2 ms ? os53 d clk clko stability (2) (period jitter or cumulative) -0.25 ? +0.25 % measured over 100 ms period note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by cl ock-cycle measurements. to get the effective jitter for individual time-bases on communicat ion clocks, use the following formula: for example, if sysclk = 80 mhz and spi bit rate = 20 mhz, the effective jitter is as follows: effectivejitter d clk sysclk communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 80 20 ----- - ------------- - d clk 2 ------------- - == table 31-19: internal frc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. characteristics min. typical max. units conditions internal frc accuracy @ 8.00 mhz (1) for pic32mx575/675/695/775 family devices f20a frc -2 ? +2 % ? internal frc accuracy @ 8.00 mhz (1,2) for pic32mx534/564/664/764 family devices f20b frc -0.9 ? +0.9 % ? note 1: frequency calibrated at 25c and 3.3v. the tun bits can be used to compensate for temperature drift. 2: this information is preliminary. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 197 pic32mx5xx/6xx/7xx figure 31-3: i/o timing characteristics table 31-20: internal rc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. characteristics min. typical max. units conditions lprc @ 31.25 khz (1) f21 lprc -15 ? +15 % ? note 1: change of lprc frequency as v dd changes. note: refer to figure 31-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31 do32 table 31-21: i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (2) min. typical (1) max. units conditions do31 t io r port output rise time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v do32 t io f port output fall time ? 5 15 ns v dd < 2.5v ?510nsv dd > 2.5v di35 t inp intx pin high or low time 10 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t sysclk ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 198 ? 2009-2011 microchip technology inc. figure 31-4: power-on reset timing characteristics v dd v por note 1: the power-up period will be extended if the power-up sequence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) sy10 cpu starts fetching code clock sources = (hs, h spll, xt, xtpll and s osc ) v dd v por sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (note 1) (note 1) clock sources = (frc, frcdiv, frcdi v16, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 199 pic32mx5xx/6xx/7xx figure 31-5: external reset timing characteristics table 31-22: resets timing ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled ?400600 s -40c to +85c sy01 t pwrt power-up period external v core applied (power-up timer active) 48 64 80 ms -40c to +85c sy02 t sysdly system delay period: time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. ? 1 s + 8 sysclk cycles ? ? -40c to +85c sy20 t mclr mclr pulse width (low) ? 2 ? s -40c to +85c sy30 t bor bor pulse width (low) ? 1 ? s -40c to +85c note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. characterized by design but not tested. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, f rcdiv, frcdiv16, frcpll , ec, ecpll and lprc) clock sources = (hs, h spll, xt, xtpll and s osc ) (t sysdly ) sy02 (t sysdly ) sy02 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 200 ? 2009-2011 microchip technology inc. figure 31-6: timer1, 2, 3, 4, 5 externa l clock timing characteristics note: refer to figure 31-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 31-23: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (2) min. typical max. units conditions ta10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, with prescaler 10 ? ? ns ? ta15 t tx ptxck input period synchronous, with prescaler [(greater of 25 ns or 2 t pb )/n] + 30 ns ??nsv dd > 2.7v [(greater of 25 ns or 2 t pb )/n] + 50 ns ??nsv dd < 2.7v asynchronous, with prescaler 20 ? ? ns v dd > 2.7v (note 3) 50 ? ? ns v dd < 2.7v (note 3) os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 ? 100 khz ? ta20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: timer1 is a type a. 2: this parameter is characterized, but not tested in manufacturing. 3: n = prescale value (1, 8, 64, 256). free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 201 pic32mx5xx/6xx/7xx figure 31-7: input capture (capx) timing characteristics table 31-24: timer2, 3, 4, 5 external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions tb10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 n = prescale value (1, 2, 4, 8, 16, 32, 64, 256) tb11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 tb15 t tx ptxck input period synchronous, with prescaler [(greater of [(25 ns or 2 t pb )/n] + 30 ns ?nsv dd > 2.7v [(greater of [(25 ns or 2 t pb )/n] + 50 ns ?nsv dd < 2.7v tb20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: these parameters are characterized, but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 31-1 for load conditions. table 31-25: input capture module timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. ic15 t cc p icx input period [(25 ns or 2 t pb )/n] + 50 ns ?ns ? note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 202 ? 2009-2011 microchip technology inc. figure 31-8: output compare module (ocx) timing characteristics table 31-26: output compare module timing requirements figure 31-9: ocx/pwm module timing characteristics ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ? ? ? ns see parameter do32 oc11 t cc r ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 31-1 for load conditions. or pwm mode) ocfa/ocfb ocx oc20 oc15 note: refer to figure 31-1 for load conditions. ocx is tri-stated table 31-27: simple ocx/pwm mode timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 50 ns ? oc20 t flt fault input pulse width 50 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 203 pic32mx5xx/6xx/7xx figure 31-10: spix module master mode (cke = 0 ) timing characteristics table 31-28: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2 ) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (3) t sck /2 ??ns ? sp20 t sc f sckx output fall time (4) ???ns see parameter do32 sp21 t sc r sckx output rise time (4) ? ?? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ?? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ?? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ?? 15 ns v dd > 2.7v ?? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ??ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 31-1 for load conditions. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 204 ? 2009-2011 microchip technology inc. figure 31-11: spix module master mode (cke = 1 ) timing characteristics table 31-29: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time (3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (3) t sck /2 ? ? ns ? sp20 t sc f sckx output fall time (4) ? ? ? ns see parameter do32 sp21 t sc r sckx output rise time (4) ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ??15nsv dd > 2.7v ??20nsv dd < 2.7v sp36 t do v2 sc , t do v2 sc l sdox data output setup to first sckx edge 15 ? ? ns ? sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 31-1 for load conditions. sp11 sp10 sp21 sp20 sp40 sp41 sp20 sp21 msb in free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 205 pic32mx5xx/6xx/7xx figure 31-12: spix module slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 31-1 for load conditions. sdi x msb in table 31-30: spix module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v- te m p param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? ? ? ns see parameter do32 sp73 t sc r sckx input rise time ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? ? 15 ns v dd > 2.7v ? ? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 175 ? ? ns ? sp51 t ss h2 do z ssx to sdox output high-impedance (3) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 206 ? 2009-2011 microchip technology inc. figure 31-13: spix module slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp40 sp41 note: refer to figure 31-1 for load conditions. sp50 sp70 sp35 table 31-31: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? 5 10 ns ? sp73 t sc r sckx input rise time ? 5 10 ns ? sp30 t do f sdox data output fall time (4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? ? 20 ns v dd > 2.7v ? ? 30 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input 175 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 207 pic32mx5xx/6xx/7xx sp51 t ss h2 do z ssx to sdo x output high-impedance (4) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ??ns ? sp60 t ss l2 do v sdox data output valid after ssx edge ? ? 25 ns ? table 31-31: spix module slave mode (cke = 1 ) timing requirements (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 208 ? 2009-2011 microchip technology inc. figure 31-14: i2cx bus start/stop bits timing characteristics (master mode) figure 31-15: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 31-1 for load conditions. im30 im31 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 31-1 for load conditions. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 209 pic32mx5xx/6xx/7xx table 31-32: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (2) t pb * (brg + 2) ? s? im11 t hi : scl clock high time 100 khz mode t pb * (brg + 2) ? s? 400 khz mode t pb * (brg + 2) ? s? 1 mhz mode (2) t pb * (brg + 2) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) 100 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (2) 0 0.3 s im30 t su : sta start condition setup time 100 khz mode t pb * (brg + 2) ? ns only relevant for repeated start condition 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im31 t hd : sta start condition hold time 100 khz mode t pb * (brg + 2) ? ns after this period, the first clock pulse is generated 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im33 t su : sto stop condition setup time 100 khz mode t pb * (brg + 2) ? ns ? 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im34 t hd : sto stop condition 100 khz mode t pb * (brg + 2) ? ns ? hold time 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode (2) t pb * (brg + 2) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ? 350 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay (3) 52 312 ns ? note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 210 ? 2009-2011 microchip technology inc. figure 31-16: i2cx bus start/stop bits timing characteristics (slave mode) figure 31-17: i2cx bus data timing characteristics (slave mode) is34 sclx sdax start condition stop condition is33 note: refer to figure 31-1 for load conditions. is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 31-1 for load conditions. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 211 pic32mx5xx/6xx/7xx table 31-33: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s pbclk must operate at a minimum of 800 khz 400 khz mode 0.6 ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode (1) 0.5 ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?100ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ?300ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4700 ? ns only relevant for repeated start condition 400 khz mode 600 ? ns 1 mhz mode (1) 250 ? ns is31 t hd : sta start condition hold time 100 khz mode 4000 ? ns after this period, the first clock pulse is generated 400 khz mode 600 ? ns 1 mhz mode (1) 250 ? ns is33 t su : sto stop condition setup time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 600 ? ns is34 t hd : sto stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf ? note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 212 ? 2009-2011 microchip technology inc. figure 31-18: can module i/o timing characteristics table 31-34: can module i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ? ? ? ns see parameter d032 ca11 tior port output rise time ? ? ? ns see parameter d031 ca20 tcwf pulse width to trigger can wake-up filter 700 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. citx pin (output) ca10 ca11 old value new value ca20 cirx pin (input) free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 213 pic32mx5xx/6xx/7xx table 31-35: ethernet module specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. characteristic min. typical max. units conditions miim timing requirements et1 mdc duty cycle 40 ? 60 % ? et2 mdc period 400 ? ? ns ? et3 mdio output delay 10 ? 10 ns ? et4 mdio input delay 0 ? 300 ns ? mii timing requirements et5 tx clock frequency ? 25 ? mhz ? et6 tx clock duty cycle 35 ? 65 % ? et7 etxdx, eten, etxerr delay 0 ? 25 ns ? et8 rx clock frequency ? 25 ? mhz ? et9 rx clock duty cycle 35 ? 65 % ? et10 erxdx, erxdv, erxerr delay 10 ? 30 ns ? rmii timing requirements et11 reference clock frequency ? 50 ? mhz ? et12 reference clock duty cycle 35 ? 65 % ? et13 etxdx, eten, delay 2 ? 16 ns ? et14 erxdx, erxdv, erxerr delay 2 ? 16 ns ? free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 214 ? 2009-2011 microchip technology inc. table 31-36: adc module specifications (5) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.5 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ?v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.0 ? av dd v (note 1) ad05a 2.5 ? 3.6 v v refh = av dd (note 3) ad06 v refl reference voltage low av ss ?v refh ? 2.0 v (note 1) ad07 v ref absolute reference voltage (v refh ? v refl ) 2.0 ? av dd v (note 3) ad08 i ref current drain ? 250 ? 400 3 a a adc operating adc off analog input ad12 v inh -v inl full-scale input span v refl ?v refh v? ad13 v inl absolute v inl input voltage av ss ? 0.3 ? av dd /2 v ? ad14 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ? ad15 leakage current ? +/- 0.001 +/-0.610 av inl = av ss = v refl = 0v, av dd = v refh = 3.3v source impedance = 10 k ad17 r in recommended impedance of analog voltage source ??5k (note 1) adc accuracy ? measurements with external v ref +/v ref - ad20c nr resolution 10 data bits bits ? ad21c inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v (note 2) ad23c g err gain error > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24n e off offset error > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 3.3v ad25c ? monotonicity ? ? ? ? guaranteed note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sinewave. 5: for pic32mx534/564/664/764 devices, data provided in this table is preliminary. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 215 pic32mx5xx/6xx/7xx adc accuracy ? measurements with internal v ref +/v ref - ad20d nr resolution 10 data bits bits (note 3) ad21d inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad22d dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (notes 2,3) ad23d g err gain error > -4 ? < 4 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad24d e off offset error > -2 ? < 2 lsb v inl = av ss = 0v, av dd = 2.5v to 3.6v (note 3) ad25d ? monotonicity ? ? ? ? guaranteed dynamic performance ad31b sinad signal to noise and distortion 55 58.5 ? db (notes 3,4) ad34b enob effective number of bits 9.0 9.5 ? bits (notes 3,4) table 31-36: adc module specifications (5) (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sinewave. 5: for pic32mx534/564/664/764 devices, data pr ovided in this table is preliminary. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 216 ? 2009-2011 microchip technology inc. table 31-37: 10-bit adc conversion rate parameters (2) standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp adc speed t ad minimum sampling time mininum r s maximum v dd adc channels configuration 1 msps to 400 ksps (1) 65 ns 132 ns 500 3.0v to 3.6v up to 400 ksps 200 ns 200 ns 5.0 k 2.5v to 3.6v up to 300 ksps 200 ns 200 ns 5.0 k 2.5v to 3.6v note 1: external v ref - and v ref + pins must be used for correct operation. 2: these parameters are characterized, but not tested in manufacturing. v ref -v ref + adc an x sha ch x v ref -v ref + adc an x sha ch x an x or v ref - or av ss or av dd v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 217 pic32mx5xx/6xx/7xx table 31-38: analog-to-digital co nversion timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions clock parameters ad50 t ad analog-to-digital clock period (2) 65 ? ? ns see table 31-37 conversion rate ad55 tconv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate (sampling speed) ? ? 1000 ksps av dd = 3.0v to 3.6v ? ? 400 ksps av dd = 2.5v to 3.6v ad57 t samp sample time 1 t ad ???t samp must be 132 ns timing parameters ad60 tpcs conversion start from sample trigger (3) ? 1.0 t ad ? ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 tpss sample start from setting sample (samp) bit 0.5 t ad ? 1.5 t ad ?? ad62 tcss conversion completion to sample start (asam = 1 ) (3) ? 0.5 t ad ?? ? ad63 tdpu time to stabilize analog stage from analog-to-digital off to analog-to-digital on (3) ?? 2 s? note 1: these parameters are characterized, but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 3: characterized by design but not tested. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 218 ? 2009-2011 microchip technology inc. figure 31-19: analog-to-digital co nversion (10-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ad60 conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in section 17. ?10-bi t a/d converter? (ds61104) of the 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 ch0_samp eoc 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution ?pic32 family reference manual? . free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 219 pic32mx5xx/6xx/7xx figure 31-20: analog-to-digital conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp set adon adclk instruction samp ch0_dischrg conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. ad50 ch0_samp eoc 7 3 ad55 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. t samp t conv 3 4 execution t samp is described in section 17. ? 10-bit a/d converter? (ds61104) of the ?pic32 family reference manual . free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 220 ? 2009-2011 microchip technology inc. figure 31-21: parallel slave port timing cs rd wr pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 31-39: parallel sl ave port requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions ps1 tdtv2wrh data in valid before wr or cs inactive (setup time) 20 ? ? ns ? ps2 twrh2dti wr or cs inactive to data-in invalid (hold time) 40 ? ? ns ? ps3 trdl2dtv rd and cs active to data-out valid ? ? 60 ns ? ps4 trdh2dti rd active or cs inactive to data-out invalid 0 ? 10 ns ? ps5 tcs cs active time t pb + 40 ? ? ns ? ps6 t wr wr active time t pb + 25 ? ? ns ? ps7 t rd rd active time t pb + 25 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 221 pic32mx5xx/6xx/7xx figure 31-22: parallel master port read timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmrd pmcs<2:1> pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 table 31-40: parallel master port read timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions pm1 t lat pmall/pmalh pulse width ? 1 t pb ?? ? pm2 t adsu address out valid to pmall/pmalh in valid (address setup time) ?2 t pb ?? ? pm3 t adhold pmall/pmalh invalid to address out invalid (address hold time) ?1 t pb ?? ? pm4 t ahold pmrd inactive to address out invalid (address hold time) 5??ns ? pm5 t rd pmrd pulse width ? 1 t pb ?? ? pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 15 ? ? ns ? pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) ?80?ns ? note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 222 ? 2009-2011 microchip technology inc. figure 31-23: parallel master port write timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmwr pmcs<2:1> pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 table 31-41: parallel master po rt write timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions pm11 t wr pmwr pulse width ? 1 t pb ?? ? pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) ?2 t pb ?? ? pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) ?1 t pb ?? ? note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 223 pic32mx5xx/6xx/7xx table 31-42: otg electrical specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions usb313 v usb usb voltage 3.0 ? 3.6 v voltage on v usb must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ? ? 0.8 v ? usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v ? usb318 v difs differential input sensitivity ? ? 0.2 v the difference between d+ and d- must exceed this value while vcm is met usb319 vcm differential common mode range 0.8 ? 2.5 v ? usb320 z out driver output impedance 28.0 ? 44.0 ? usb321 v ol voltage output low 0.0 ? 0.3 v 14.25 k load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 14.25 k load connected to ground note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 224 ? 2009-2011 microchip technology inc. figure 31-24: ejtag timing characteristics t tckeye t tckhigh t tcklow t rf t rf t rf t rf t tsetup t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms table 31-43: ejtag timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +105c for v-temp param. no. symbol description (1) min. max. units conditions ej1 t tckcyc tck cycle time 25 ? ns ? ej2 t tckhigh tck high time 10 ? ns ? ej3 t tcklow tck low time 10 ? ns ? ej4 t tsetup tap signals setup time before rising tck 5?ns ? ej5 t thold tap signals hold time after rising tck 3?ns ? ej6 t tdoout tdo output delay time from falling tck ?5ns ? ej7 t tdozstate tdo 3-state delay time from falling tck ?5ns ? ej8 t trstlow trst low time 25 ? ns ? ej9 t rf tap signals rise/fall time, all input and output ??ns ? note 1: these parameters are characterized, but not tested in manufacturing. free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 225 pic32mx5xx/6xx/7xx 32.0 packaging information 32.1 package marking information pic32mx575f 512h-80i/pt 0510017 3 e legend: xx...x customer-spec ific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx575f 512l-80i/pt 0510017 3 e 100-lead tqfp (14x14x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx575f 512l-80i/pf 0510017 3 e free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 226 ? 2009-2011 microchip technology inc. 32.1 package marking information (continued) xxxxxxxxxx 64-lead qfn (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx575f example 512h-80i/mr 0510017 3 e xxxxxxxxxx 121-lead xbga (10x10x1.1 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx575f example 512h-80i/bg 0510017 3 e free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 227 pic32mx5xx/6xx/7xx 32.2 package details the following sections give the technical details of the packages.

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pic32mx5xx/6xx/7xx ds61156g-page 228 ? 2009-2011 microchip technology inc.

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? 2009-2011 microchip tec hnology inc. ds61156g-page 229 pic32mx5xx/6xx/7xx

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pic32mx5xx/6xx/7xx ds61156g-page 230 ? 2009-2011 microchip technology inc.

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? 2009-2011 microchip tec hnology inc. ds61156g-page 231 pic32mx5xx/6xx/7xx

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pic32mx5xx/6xx/7xx ds61156g-page 232 ? 2009-2011 microchip technology inc.

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? 2009-2011 microchip tec hnology inc. ds61156g-page 233 pic32mx5xx/6xx/7xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 234 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 235 pic32mx5xx/6xx/7xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 236 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 237 pic32mx5xx/6xx/7xx note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 238 ? 2009-2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 239 pic32mx5xx/6xx/7xx appendix a: migrating from pic32mx3xx/4xx to pic32mx5xx/6xx/7xx devices this appendix provides an overview of considerations for migrating from pic32mx3xx/4xx devices to the pic32mx5xx/6xx/7xx family of devices. the code developed for the pic32mx3xx/4xx devices can be ported to the pic32mx5xx/6xx/7xx devices after making the appropriate changes outlined below. a.1 dma pic32mx5xx/6xx/7xx devices do not support stopping dma transfers in idle mode. a.2 interrupts pic32mx5xx/6xx/7xx devices have persistent interrupts for some of the peripheral modules. this means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. for example, to clear a uart receive interrupt, the user application must first read the uart receive register to clear the interrupt condition and then clear the associated uxif flag to clear the pending uart interrupt. in other words, the uxif flag cannot be cleared by software until the uart receive register is read. table a-1 outlines the peripherals and associated interrupts that are implemented differently on pic32mx5xx/6xx/7xx versus pic32mx3xx/4xx devices. in addition, on the spi module, the irq numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25. table a-1: pic32mx3xx/4xx versus pic32m x5xx/6xx/7xx interrupt implementation differences module interrupt implementation input capture to clear an interrupt source, read the buffer result (icxbuf) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ici<1:0> bits). spi receive and transmit interrupts are controlled by the srxisel<1:0> and stxisel<1:0> bits, respectively. to clear an interrupt source, data must be written to, or read from, the spixbuf register to obtain the number of data to receive/transmit below the level specified by the srxisel<1:0> and stxisel<1:0> bits. uart tx interrupt will be generated as soon as the uart module is enabled. receive and transmit interrupts are controlled by the urxisel<1:0> and utxisel<1:0> bits, respectively. to clear an interrupt source, data must be read from, or written to, the uxrxreg or uxtxreg registers to obtain the number of data to receive/transmit below the level specified by the urxisel<1:0> and utxisel<1:0> bits. adc all samples must be read from the result regi sters (adc1bufx) to clear the interrupt source. pmp to clear an interrupt source, read the parallel master port data input/output (pmdin/pmdout) register. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 240 ? 2009-2011 microchip technology inc. appendix b: revision history revision a (august 2009) this is the initial released version of this document. revision b (november 2009) the revision includes the following global update: ? added note 2 to the shaded table that appears at the beginning of each chapter. this new note pro- vides information regarding the availability of regis- ters and their associated bits. other major changes are referenced by their respective chapter/section in ta b l e b - 1 . table b-1: major section updates section name update description ? high-performance, usb, can and ethernet 32-bit flash microcontrollers ? added the following devices: - pic32mx575f256l - pic32mx695f512l - pic32mx695f512h the 100-pin tqfp pin diagrams have been updated to reflect the current pin name locations (see the ? pin diagrams ? section). added the 121-pin ball grid array (xbga) pin diagram. updated ta b l e 1 : ? pic32 usb and can ? features ? added the following tables: - ta b l e 4 : ? pin names: pic32mx534f064l, pic32mx564f064l, pic32mx564f128l, pic32mx575f256l and pic32mx575f512l devices ? - ta b l e 5 : ? pin names: pic32mx664f064l, pic32mx664f128l, pic32mx675f256l, pic32mx675f512l and pic32mx695f512l devices ? - ta b l e 6 : ? pin names: pic32mx775f256l, pic32mx775f512l and pic32mx795f512l devices ? updated the following pins as 5v tolerant: - 64-pin qfn: pin 36 (d-/rg3) and pin 37 (d+/rg2) - 64-pin tqfp: pin 36 (d-/rg3) and pin 37 (d+/rg2) - 100-pin tqfp: pin 56 (d-/rg3) and pin 57 (d+/rg2) 2.0 ?guidelines for getting started with 32-bit mi crocontrollers? removed the last sentence of 2.3.1 ?internal regulator mode? . removed section 2.3.2 ?external regulator mode? free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 241 pic32mx5xx/6xx/7xx 4.0 ?memory organization? updated all register tables to include the virtual address and all resets columns. updated the title of figure 4-4 to include the pic32mx575f256l device. updated the title of figure 4-6 to include the pic32mx695f512l and pic32mx695f512h devices. also changed pic32mx795f512l to pic32mx795f512 h . updated the title of ta b l e 4 - 3 to include the pic32mx695f512h device. updated the title of ta b l e 4 - 5 to include the pic32mx575f5256l device. updated the title of ta b l e 4 - 6 to include the pic32mx695f512l device. reversed the order of ta b l e 4 - 11 and table 4-12 . reversed the order of ta b l e 4 - 1 4 and ta b l e 4 - 1 5 . updated the title of ta b l e 4 - 1 5 to include the pic32mx575f256l and pic32mx695f512l devices. updated the title of ta b l e 4 - 4 5 to include the pic32mx575f256l device. updated the title of ta b l e 4 - 4 7 to include the pic32mx695f512h and pic32mx695f512l devices. 12.0 ?i/o ports? updated the second paragraph of 12.1.2 ?digital inputs? and removed table 12-1. 22.0 ?10-bit analog-to-digital converter (adc)? updated the adc conversion clock period block diagram (see figure 22-2 ). 28.0 ?special features? removed references to the envreg pin in 28.3 ?on-chip voltage regulator? . updated the first sentence of 28.3.1 ?on-chip regulator and por? and 28.3.2 ?on-chip regulator and bor? . updated the connections for the on-chip regulator (see figure 28-2 ). 31.0 ?electrical characteristics? updated the absolute maximum ratings and added note 3. added thermal packaging characteristics for the 121-pin xbga package (see table 31-3 ). updated the operating current (i dd ) dc characteristics (see ta b l e 3 1 - 5 ). updated the idle current (i idle ) dc characteristics (see table 31-6 ). updated the power-down current (i pd ) dc characteristics (see table 31-7 ). removed note 1 from the program flash memory wait state characteristics (see table 31-12 ). updated the spix module slave mode (cke = 1 ) timing characteristics, changing sp52 to sp35 between the msb and bit 14 on sdox (see figure 31-13 ). 32.0 ?packaging information? added the 121-pin xbga package marking information and package details. ? product identifi cation system ? added the definition for bg (121-lead 10x10x1.1 mm, xbga). added the definition for speed. table b-1: major section updates (continued) section name update description free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 242 ? 2009-2011 microchip technology inc. revision c (february 2010) the revision includes the following updates, as described in table b-2 : table b-2: major section updates section name update description ? high-performance, usb, can and ethernet 32-bit flash microcontrollers ? added the following devices: ? pic32mx675f256h ? pic32mx775f256h ? pic32mx775f512h ? pic32mx675f256l ? pic32mx775f256l ? pic32mx775f512l added the following pins: ?erefclk ? ecrsdv ? aerefclk ? aecrsdv added the erefclk and ecrsdv pins to ta b l e 5 and ta b l e 6 . 1.0 ?device overview? updated the pin number pinout i/o descriptions for the following pin names in table 1-1 : added the following pins to the pinout i/o descriptions table ( ta b l e 1 - 1 ): ?erefclk ? ecrsdv ? aerefclk ? aecrsdv 4.0 ?memory organization? added new devices and updated the virtual and physical memory map values in figure 4-4 . added new devices to figure 4-5 . added new devices to the following register maps: ? table 4-3 , ta b l e 4 - 4 , ta b l e 4 - 6 and table 4-7 (interrupt register maps) ? table 4-12 (i2c2 register map) ? table 4-15 (spi1 register map) ? table 4-24 through ta b l e 4 - 3 5 (porta-portg register maps) ? table 4-36 and ta b l e 4 - 3 7 (change notice and pull-up register maps) ? table 4-45 (can1 register map) ? table 4-46 (can2 register map) ? table 4-47 (ethernet controller register map) changed the bits named poscmd to poscmod in table 4-42 (device configuration word summary). 28.0 ?special features? changed all references of poscmd to poscmod in the device configuration word 1 register (see register 28-2 ). appendix a: ?migrating from pic32mx3xx/4xx to pic32mx5xx/6xx/7xx devices? added the new section appendix . ?scl3 ?scl5 ?rtcc ?c1out ?sda3 ?sda5 ?cv ref -?c2in- ?scl2 ?tms ?cv ref +?c2in+ ?sda2 ?tck ?cv refout ?c2out ? scl4 ? tdi ? c1in- ? pma0 ? sda4 ? tdo ? c1in+ ? pma1 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 243 pic32mx5xx/6xx/7xx revision d (may 2010) the revision includes the following updates, as described in table b-3 : table b-3: major section updates section name update description ? high-performance, usb, can and ethernet 32-bit flash microcontrollers ? updated the initial flash memory range to 64k. updated the initial sram memory range to 16k. added the following devices (see ta b l e 1 , ta b l e 2 , ta b l e 3 and the pin diagrams): ? pic32mx534f064h ? PIC32MX564F064H ? pic32mx664f064h ? pic32mx564f128h ? pic32mx664f128h ? pic32mx764f128h ? pic32mx534f064l ? pic32mx564f064l ? pic32mx664f064l ? pic32mx564f128l ? pic32mx664f128l ? pic32mx764f128l 4.0 ?memory organization? added new memory maps ( figure 4-1 , figure 4-2 and figure 4-3 ). the bit named i2csif was changed to i2c1sif and the bit named i2cbif was changed to i2c1bif in the interrupt register map tables ( ta b l e 4 - 2 , table 4-3 , table 4-4 , ta b l e 4 - 5 , ta b l e 4 - 6 and table 4-7 ) added the following devices to the interrupt register map ( ta b l e 4 - 2 ): ? pic32mx534f064h ? PIC32MX564F064H ? pic32mx564f128h added the following devices to the interrupt register map ( ta b l e 4 - 3 ): ? pic32mx664f064h ? pic32mx664f128h added the following device to the interrupt register map ( ta b l e 4 - 4 ): ? pic32mx764f128h added the following devices to the interrupt register map ( ta b l e 4 - 5 ): ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l added the following devices to the interrupt register map ( ta b l e 4 - 6 ): ? pic32mx664f064l ? pic32mx664f128l added the following device to the interrupt register map ( ta b l e 4 - 7 ): ? pic32mx764f128l free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 244 ? 2009-2011 microchip technology inc. 4.0 ?memory organization? (continued) made the following bit name changes in the i2c1, i2c3, i2c4 and i2c5 register map ( ta b l e 4 - 11 ): ? i2c3brg sfr: i2c1brg was changed to i2c3brg ? i2c4brg sfr: i2c1brg was changed to i2c4brg ? i2c5brg sfr: i2c1brg was changed to i2c5brg ? i2c4trn sfr: i2ct1data was changed to i2ct2adata ? i2c4rcv sfr: i2cr2data was changed to i2cr2adata ? i2c5trn sfr: i2ct1data was changed to i2ct3adata ? i2c5rcv sfr: i2cr1data was changed to i2cr3adata added the rtsmd bit and uen<1:0> bits to the uart1a, uart1b, uart2a, uart2b, uart3a and uart3b register map ( table 4-13 ) added the sidl bit to the dma global register map ( ta b l e 4 - 1 7 ). changed the cm bit to cmr in the system control register map ( ta b l e 4 - 2 3 ). added the following devices to the i2c2, spi1, porta, portc, portd, porte, portf, portg, change notice and pull-up register maps ( ta b l e 4 - 1 2 , table 4-14 , ta b l e 4 - 2 4 , ta b l e 4 - 2 7 , ta b l e 4 - 2 9 , table 4-31 , table 4-33 , table 4-35 and ta b l e 4 - 3 6 ): ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l ? pic32mx664f064l ? pic32mx664f128l ? pic32mx764f128l added the following devices to the portc, portd, porte, portf, portg, change notice and pull-up register maps ( ta b l e 4 - 2 6 , ta b l e 4 - 2 8 , ta b l e 4 - 3 0 , table 4-32 , ta b l e 4 - 3 4 and table 4-37 ): ? pic32mx534f064h ? PIC32MX564F064H ? pic32mx564f128h ? pic32mx664f064h ? pic32mx664f128h ? pic32mx764f128h added the following devices to the can1 register map ( table 4-45 ): ? pic32mx534f064h ? PIC32MX564F064H ? pic32mx564f128h ? pic32mx764f128h ? pic32mx534f064l ? pic32mx564f064l ? pic32mx564f128l ? pic32mx764f128l added the following devices to the ethernet controller register map ( ta b l e 4 - 4 7 ): ? pic32mx664f064h ? pic32mx664f128h ? pic32mx764f128h ? pic32mx664f064l ? pic32mx664f128l ? pic32mx764f128l table b-3: major section updates (continued) section name update description free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 245 pic32mx5xx/6xx/7xx 31.0 ?electrical characteristics? updated the typical and maximum dc characteristics: operating current (i dd ) in table 31-5 . updated the typical and maximum dc characteristics: idle current (i idle ) in table 31-6 . updated the typical and maximum dc characteristics: power-down current (i pd ) in table 31-7 . added dc characteristics: program memory parameters d130a and d132a in table 31-11 . added the internal voltage reference parameter (d305) to the comparator specifications in table 31-13 . table b-3: major section updates (continued) section name update description free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 246 ? 2009-2011 microchip technology inc. revision e (july 2010) minor corrections were incorporated throughout the document. revision f (december 2010) the revision includes the following global update: v cap /v ddcore has been changed to: v cap /v core other major changes are referenced by their respective chapter/section in ta b l e b - 4 : table b-4: section updates section name update description high-performance, usb, can and ethernet 32-bit flash microcontrollers removed the following analog feature: fv tolerant input pins (digital pins only) updated the term lin 1.2 support as lin support for the peripheral feature: six uart modules with: rs-232, rs-485, and lin support 1.0 ?device overview? updated the value of 64-pin qfn/tqfp pin number for the following pin names: pma0, pma1 and ecrsdv 4.0 ?memory organization? the following register map tables were updated: ? table 4-2 : - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8-24/10 to sripl<2:0> in intstat - changed bits 25/9/-24/8 to u5is<1:0> in ipc12 - added note 2 ? table 4-3 through ta b l e 4 - 7 : - changed bits 24/8-24/10 to sripl<2:0> in intstat - changed bits 25/9-24/8 to u5is<1:0> in ipc12 ? table 4-3 : - changed bits 24/8 to i2c5bif in ifs1 - added note 2 ? table 4-4 : - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8 to i2c5bie in iec1 - added note 2 references ? table 4-5 : - changed bits 24/8 to i2c5bif in ifs1 - changed bits 24/8 to i2c5bie in iec1 - added note 2 references ? table 4-6 : - changed bit 24/8 to i2c5bif in ifs1 - updated the bit value of bit 24/8 as i2c5bie for the iec1 register. - added note 2 ? table 4-7 : - changed bit 25/9 to i2c5sif in ifs1 - changed bit 24/8 as i2c5bif in ifs1 - changed bit 25/9 as i2c5sie in iec1 - changed bit 24/8 as i2c5bie in iec1 - added note 2 references ? added note 2 to ta b l e 4 - 8 ? updated the all resets values for the following registers in table 4-11 : i2c3con, i2c4con, i2c5con and i2c1con. ? updated the all resets values for the i2c2con register in ta b l e 4 - 1 2 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 247 pic32mx5xx/6xx/7xx 4.0 ?memory organization? (continued) ? table 4-13 : - changed register u4rg to u1brg - changed register u5rg to u3brg - changed register u6rg to u2brg ? table 4-14 : - updated the all resets values for the following registers: spi3stat, spi2stat and spi4stat ? table 4-15 : updated the all resets values for the spi1stat register ? table 4-17 : added note 2 ? table 4-19 : added note 2 ? table 4-20 : updated the all resets values for the cm1con and cm2con registers ? table 4-21 : - updated the all resets values as 0000 for the cvrcon register - updated note 2 ? table 4-38 : updated the all resets values for the pmstat register ? table 4-40 : updated the all resets values for the checon and chetag registers ? table 4-42 : updated the bit value of bit 29/13 as ??? for the devcfg3 register ? table 4-44 : - updated the note references in the entire table - changed existing note 1 to note 4 - added notes 1, 2 and 3 - changed bits 23/7 in u1pwrc to uactpnd - changed register u1ddr to u1addr - changed register u4dtp1 to u1bdtp1 - changed register u4dtp2 to u1bdtp2 - changed register u4dtp3 to u1bdtp3 ? table 4-45 : - updated the all resets values for the c1con and c1vec registers - changed bits 30/14 in c1con to frz - changed bits 27/11 in c1con to canbusy - changed bits 22/6-16/0 in c1vec to icode<6:0> - changed bits 22/6-16/0 in c1trec to rerrcnt<7:0> - changed bits 31/15-24/8 in c1trec to terrcnt<7:0> ? table 4-46 : - updated the all resets values for the c2con and c2vec registers - changed bits 30/14 in c1con to frz - changed bits 27/11 in c1con to canbusy - changed bits 22/6-16/0 in c1vec register to icode<6:0> - changed bits 22/6-16/0 in c1trec register to rerrcnt<7:0> - changed bits 31/15-24/8 in c1trec to terrcnt<7:0> table b-4: section updates (continued) section name update description free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 248 ? 2009-2011 microchip technology inc. 7.0 ?interrupt controller? ? updated the following interrupt sources in table 7-1 : - changed ic2am ? i2c4 master event to: ic4m ? i2c4 master event - changed ic3am ? i2c5 master event to: ic5m ? i2c4 master event - changed u1e ? uart1a error to: u1e ? uart1 error - changed u4e ? uart1b error to: u4e ? uart4 error - changed u1rx ? uart1a receiver to: u1rx ? uart1 receiver - changed u4rx ? uart1b receiver to: u4rx ? uart4 receiver - changed u1tx ? uart1a transmitter to: u1tx ? uart1 transmitter - changed u4tx ? uart1b transmitter to: u4tx ? uart4 transmitter - changed u6e ? uart2b error to: u6e ? uart6 error - changed u6rx ? uart2b receiver to: u6rx ? uart6 receiver - changed u6tx ? uart2b transmitter to: u6tx ? uart6 transmitter - changed u5e ? uart3b error to: u5e ? uart5 error - changed u5rx ? uart3b receiver to: u5rx ? uart5 receiver - changed u5tx ? uart3b transmitter to: u5tx ? uart5 transmitter 8.0 ?oscillator configuration? updated figure 8-1 16.0 ?output compare? updated figure 16-1 24.0 ?ethernet controller? added a note on using the ethernet controller pins (see note above table 24-3 ) 26.0 ?comparator voltage reference (cv ref )? updated the note in figure 26-1 28.0 ?special features? updated the bit description for bit 10 in register 28-2 added notes 1 and 2 to register 28-4 31.0 ?electrical characteristics? updated the absolute maximum ratings: ? voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v - 0.3v to +3.6v was updated ? voltage on v bus with respect to v ss - 0.3v to +5.5v was added updated the maximum value of dc16 as 2.1 in table 31-4 updated the typical values for the following parameters: dc20b, dc20c, dc21c, dc22c and dc23c (see ta b l e 3 1 - 5 ) updated table 31-11 : ? removed the following dc characteristics: programming temperature 0c ta +70c (25c recommended) ? updated the minimum value for the parameter number d131 as 2.3 ? removed the conditions for the following parameter numbers: d130, d131, d132, d135, d136 and d137 ? updated the condition for the parameter number d130a and d132a updated the minimum, typical and maximum values for parameter d305 in table 31-13 added note 2 to table 31-18 updated the minimum and maximum values for parameter f20b (see table 31-19 ) updated the following figures: ? figure 31-4 ? figure 31-9 ? figure 31-19 ? figure 31-20 appendix a: ?migrating from pic32mx3xx/4xx to pic32mx5xx/ 6xx/7xx devices? removed the a.3 pin assignments sub-section. table b-4: section updates (continued) section name update description free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 249 pic32mx5xx/6xx/7xx revision g (may 2011) the revision includes the following global update: ? all references to v ddcore /v cap have been changed to: v core /v cap ? added references to the new v-temp temperature range: -40oc to +105oc this revision also includes minor typographical and formatting changes throughout the data sheet text. major updates are referenced by their respective section in the following table. table b-5: major section updates section name update description high-performance, usb, can and ethernet 32-bit flash microcontrollers removed the shading for all d- and d+ pins in all pin diagrams. 1.0 ?device overview? updated the v bus description in table 1-1 . 2.0 ?guidelines for getting started with 32-bit microcontrollers? added 2.11 ?referenced sources? . 4.0 ?memory organization? added note 3 to the interrupt register map tables (see ta b l e 4 - 2 through ta b l e 4 - 7 . 22.0 ?10-bit analog-to-digital converter (adc)? updated the adc conversion clock period block diagram (see figure 22-2 ). 26.0 ?comparator voltage reference (cv ref )? updated the comparator voltage reference block diagram (see figure 26-1 ). 28.0 ?special features? removed the second paragraph from 28.3.1 ?on-chip regulator and por? . 31.0 ?electrical characteristics? added the new v-temp temperature range (-40oc to +105oc) to the heading of all specification tables. updated the ambient temperature under bias, updated the voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v, and added voltage on v bus with respect to vss in absolute maximum ratings . added the characteristic, dc5a to operating mips vs. voltage (see table 31-1 ). updated or added the following parameters to the operating current (i dd ) dc characteristics: dc20, dc20b, dc23, and dc23b (see table 31-5 ). added the following parameters to the idle current (i idle ) dc characteristics: dc30b, dc33b, dc34c, dc35c, and dc36c (see table 31-6 ). added the following parameters to the power-down current (i pd ) dc characteristics: dc40g, dc40h, dc40i, and dc41g, (see table 31-7 ). added parameter im51 and note 3 to the i2cx bus data timing requirements (master mode) (see table 31-32 ). updated the 10-bit adc conversion rate parameters (see table 31-37 ). updated parameter ad57 (t samp ) in the analog-to-digital conversion timing requirements (see table 31-38 ). 32.0 ?packaging information? updated the 64-lead plastic quad flat, no lead package (mr) ? 9x9x0.9 mm body [qfn] packing diagram. product identifi cation system added the new v-temp (v) temperature information. free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 250 ? 2009-2011 microchip technology inc. notes: free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 251 pic32mx5xx/6xx/7xx index a ac characteristics ............................................................ 194 10-bit conversion rate parameters.......................... 216 adc specifications ................................................... 214 analog-to-digital conversion requirements............. 217 ejtag timing requirements ................................... 224 ethernet .................................................................... 213 internal frc accuracy.............................................. 196 internal rc accuracy ................................................ 197 otg electrical specifications ................................... 223 parallel master port read requirements ................. 221 parallel master port write ......................................... 222 parallel master port write requirements.................. 222 parallel slave port requirements ............................. 220 pll clock timing...................................................... 196 analog-to-digital converter (adc).................................... 153 assembler mpasm assembler................................................... 180 b block diagrams adc module.............................................................. 153 comparator i/o operating modes............................. 159 comparator voltage reference ................................ 161 connections for on-chip voltage regulator............. 174 core and peripheral modules ..................................... 31 dma .......................................................................... 129 ethernet controller.................................................... 157 i2c circuit ................................................................. 146 input capture ............................................................ 139 interrupt controller .................................................... 121 jtag programming, debugging and trace ports .... 175 mcu............................................................................ 49 output compare module........................................... 141 pic32 can module................................................... 155 pmp pinout and connections to external devices ... 149 prefetch module........................................................ 127 reset system............................................................ 119 rtcc ........................................................................ 151 spi module ............................................................... 143 timer1....................................................................... 135 timer2/3/4/5 (16-bit) ................................................. 137 typical multiplexed port structure ............................ 133 uart ........................................................................ 147 wdt and power-up timer ........................................ 173 brown-out reset (bor) and on-chip voltage regulator................................ 174 c c compilers mplab c18 .............................................................. 180 clock diagram .................................................................. 125 comparator specifications............................................................ 192 comparator module .......................................................... 159 comparator voltage reference (cvref ............................. 161 configuration bit ............................................................... 165 controller area network (can)......................................... 155 cpu module........................................................................ 43 customer change notification service ............................. 253 customer notification service........................................... 253 customer support ............................................................. 253 d dc characteristics............................................................ 184 i/o pin input specifications ...................................... 189 i/o pin output specifications.................................... 190 idle current (i idle ) .................................................... 186 operating current (i dd ) ............................................ 185 power-down current (i pd )........................................ 187 program memory...................................................... 191 temperature and voltage specifications.................. 184 development support ....................................................... 179 direct memory access (dma) controller.......................... 129 e electrical characteristics .................................................. 183 ac............................................................................. 194 errata .................................................................................. 29 ethernet controller............................................................ 157 external clock timer1 timing requirements ................................... 200 timer2, 3, 4, 5 timing requirements ....................... 201 timing requirements ............................................... 195 f flash program memory .................................................... 117 rtsp operation ....................................................... 117 i i/o ports ........................................................................... 133 parallel i/o (pio) ...................................................... 134 instruction set................................................................... 177 inter-integrated circuit (i2c) ............................................. 145 internal voltage reference specifications........................ 193 internet address ............................................................... 253 interrupt controller............................................................ 121 irg, vector and bit location .................................... 122 m mcu architecture overview ................................................ 50 coprocessor 0 registers ............................................ 52 core exception types ................................................ 53 ejtag debug support............................................... 54 power management ................................................... 54 mcu module....................................................................... 49 memory map....................................................................... 60 memory maps ............................................. 56, 57, 58, 59, 61 memory organization ......................................................... 55 layout......................................................................... 55 microchip internet web site.............................................. 253 migration pic32mx3xx/4xx to pic32mx5xx/6xx/7xx......... 239 mplab asm30 assembler, linker, librarian ................... 180 mplab integrated development environment software.. 179 mplab pm3 device programmer .................................... 182 mplab real ice in-circuit emulator system ................ 181 mplink object linker/mplib object librarian ................ 180 o open-drain configuration................................................. 134 oscillator configuration .................................................... 125 output compare ............................................................... 141 p packaging ......................................................................... 225 free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 252 ? 2009-2011 microchip technology inc. details ....................................................................... 227 marking ..................................................................... 225 parallel master port (pmp) ............................................... 149 pic32 family usb interface diagram............................... 132 pinout i/o descriptions (table) ............................................ 32 power-on reset (por) and on-chip voltage regulator ................................ 174 power-saving features..................................................... 163 cpu halted methods ................................................ 163 operation .................................................................. 163 with cpu running..................................................... 163 prefetch cache ................................................................. 127 program flash memory wait state characteristics......................................... 192 r reader response ............................................................. 254 real-time clock and calendar (rtcc)............................ 151 register maps ............................................................. 62?116 registers ddpcon (debug data port control)........................ 176 devcfg0 (device configuration word 0 ................. 166 devcfg1 (device configuration word 1 ................. 168 devcfg2 (device configuration word 2 ................. 170 devcfg3 (device configuration word 3 ................. 171 devid (device and revision id) .............................. 172 resets ............................................................................... 119 revision history ................................................................ 240 s serial peripheral interface (spi) ....................................... 143 software simulator (mplab sim)..................................... 181 special features ............................................................... 165 t timer1 module .................................................................. 135 timer2/3, timer4/5 modules ............................................. 137 timing diagrams 10-bit analog-to-digital conversion (asam = 0, ss- rc<2:0> = 000) ................................................ 218 10-bit analog-to-digital conversion (chps<1:0> = 01, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001)............................................................... 219 can i/o..................................................................... 212 ejtag ...................................................................... 224 external clock ........................................................... 194 i/o characteristics .................................................... 197 i2cx bus data (master mode) .................................. 208 i2cx bus data (slave mode) .................................... 210 i2cx bus start/stop bits (master mode)................... 208 i2cx bus start/stop bits (slave mode)..................... 210 input capture (capx) ............................................... 201 ocx/pwm................................................................. 202 output compare (ocx)............................................. 202 parallel master port read......................................... 221 parallel master port write......................................... 222 parallel slave port .................................................... 220 spix master mode (cke = 0) ................................... 203 spix master mode (cke = 1) ................................... 204 spix slave mode (cke = 0) ..................................... 205 spix slave mode (cke = 1) ..................................... 206 timer1, 2, 3, 4, 5 external clock .............................. 200 uart reception....................................................... 148 uart transmission (8-bit or 9-bit data) .................. 148 timing requirements clko and i/o ........................................................... 197 timing specifications can i/o requirements ............................................. 212 i2cx bus data requirements (master mode)........... 209 i2cx bus data requirements (slave mode)............. 211 input capture requirements..................................... 201 output compare requirements................................ 202 simple ocx/pwm mode requirements ................... 202 spix master mode (cke = 0) requirements............ 203 spix master mode (cke = 1) requirements............ 204 spix slave mode (cke = 1) requirements.............. 206 spix slave mode requirements (cke = 0).............. 205 u uart ................................................................................ 147 usb on-the-go (otg) .................................................... 131 v v cap /v core pin ................................................................ 174 voltage reference specifications..................................... 193 voltage regulator (on-chip) ............................................ 174 w watchdog timer (wdt).................................................... 173 www address ................................................................. 253 www, on-line support ..................................................... 29 free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 253 pic32mx5xx/6xx/7xx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support free datasheet http://www.datasheet-pdf.com/
pic32mx5xx/6xx/7xx ds61156g-page 254 ? 2009-2011 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds61156g pic32mx5xx/6xx/7xx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? free datasheet http://www.datasheet-pdf.com/
? 2009-2011 microchip tec hnology inc. ds61156g-page 255 pic32mx5xx/6xx/7xx product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture mx = 32-bit risc mcu core product groups 5xx = general purpose microcontroller family 6xx = general purpose microcontroller family 7xx = general purpose microcontroller family flash memory family f = flash program memory program memory size 256 = 256k 512 = 512k pin count h = 64-pin l = 100-pin speed 80 = 80 mhz temperature range i = -40c to +85c (industrial) v = -40c to +105c (v-temp) package pt = 64-lead (10x10x1 mm) tqfp (thin quad flatpack) pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pf = 100-lead (14x14x1 mm) tqfp (thin quad flatpack) mr = 64-lead (9x9x0.9 mm) qfn (plastic quad flat) bg = 121-lead (10x10x1.1 mm) xbga (plastic thin profile ball grid array) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample example: pic32mx575f256h-80i/pt: general purpose pic32, 32-bit risc mcu, 256 kb program memory, 64-pin, industrial temperature, tqfp package. microchip brand architecture flash memory family pin count product groups program memory size (kb) pic32 m x 5xx f 512 h t - 80 i / pt - xxx flash memory family speed pattern package temperature range tape and reel flag (if applicable) free datasheet http://www.datasheet-pdf.com/
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